diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-12-11 17:12:32 +0100 |
---|---|---|
committer | Angel Pons <th3fanbus@gmail.com> | 2020-12-14 10:40:51 +0000 |
commit | 68cf57cf33141edcc8b4b1250b099884e0553457 (patch) | |
tree | cc7a8d69a6fa3fe6e802fbe31f325cfd40e40d8c | |
parent | 950cdbc3e25f021cb71693fb7c27b0588da1233d (diff) | |
download | coreboot-68cf57cf33141edcc8b4b1250b099884e0553457.tar.gz coreboot-68cf57cf33141edcc8b4b1250b099884e0553457.tar.bz2 coreboot-68cf57cf33141edcc8b4b1250b099884e0553457.zip |
soc/intel/skylake: Drop always-zero ProbelessTrace dt setting
This seems to be a debugging option. Since unset devicetree options
default to zero, drop the setting. If it is needed in the future, a
user-visible Kconfig option would probably make more sense.
Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
17 files changed, 1 insertions, 19 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 0e408f808eed..43f272e5a8cc 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/skylake register "dptf_enable" = "0" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "1" register "SataMode" = "0" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index f8a92d88ded8..0e76de140f8d 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -35,7 +35,6 @@ chip soc/intel/skylake register "gen3_dec" = "0x00fc0901" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 430334af5f57..8c31f9ac706d 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -64,7 +64,6 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 4f8beefd650c..127334e1bad2 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 4fd71d5cf6d2..a14e927b0f65 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -41,7 +41,6 @@ chip soc/intel/skylake register "CmdTriStateDis" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 93836421f0c3..4bfac6d78b2a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -31,7 +31,6 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 65ecc8f3f1fd..25d720e5847d 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -31,7 +31,6 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "DspEnable" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index ec55645a8410..95632985185e 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -31,7 +31,6 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 6b58e0b04894..899990de0bb2 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake register "CmdTriStateDis" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 841823116c57..ff117c8aa260 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -41,7 +41,6 @@ chip soc/intel/skylake register "CmdTriStateDis" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 8e5caf3fb21e..6a37b8a4bcb8 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -31,7 +31,6 @@ chip soc/intel/skylake register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index f6e73c6bd69b..9fedde5db894 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/skylake register "dptf_enable" = "0" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index d8e68a2373e1..abbfda422374 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -31,7 +31,6 @@ chip soc/intel/skylake register "tcc_offset" = "5" # TCC of 95C # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "DspEnable" = "0" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 6d98772af7dc..c59df4051871 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -41,7 +41,6 @@ chip soc/intel/skylake register "dptf_enable" = "0" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 8f3e0d6bc330..44b352359df2 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -23,7 +23,6 @@ chip soc/intel/skylake register "dptf_enable" = "0" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 4d92410b6560..f4744c96314f 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -90,9 +90,6 @@ struct soc_intel_skylake_config { /* Whether to ignore VT-d support of the SKU */ int ignore_vtd; - /* Probeless Trace function */ - u8 ProbelessTrace; - /* * System Agent dynamic frequency configuration * When enabled memory will be trained at two different frequencies. diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 79fb46425d33..c826187c4b88 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -216,7 +216,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->MmioSize = 0x800; /* 2GB in MB */ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->ProbelessTrace = config->ProbelessTrace; + m_cfg->ProbelessTrace = 0; m_cfg->SaGv = config->SaGv; m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->Rmt; |