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| author | Robert Chen <robert.chen@quanta.corp-partner.google.com> | 2021-09-22 16:49:51 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-09-28 05:55:45 +0000 |
| commit | 6978a214f1bfed1975c263f2053760694040bf4f (patch) | |
| tree | 5efef3bca4b452660f9102fa7752a31031e3df96 | |
| parent | cf390d9e47f834c8adfc68cabb1df67e26b989b1 (diff) | |
| download | coreboot-6978a214f1bfed1975c263f2053760694040bf4f.tar.gz coreboot-6978a214f1bfed1975c263f2053760694040bf4f.tar.bz2 coreboot-6978a214f1bfed1975c263f2053760694040bf4f.zip | |
mb/google/dedede/var/kracko: refactor DPTF section for overrides
Refactor DPTF section of code under the kracko overridetree. This makes kracko override dptf section of dedede/baseboard, because the DPTF tool's CRT, PSV and TSR3 settings are different than expected.
BUG=b:187482019
BRANCH=dedede
TEST=Built and tested on dedede system
Change-Id: Iacc543f961a7f4652ee8583920b1794f916c7ec9
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/dedede/variants/kracko/overridetree.cb | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb index 36226de4b522..2124103fb6bf 100644 --- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb +++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb @@ -58,7 +58,63 @@ chip soc/intel/jasperlake }, }" + register "power_limits_config" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + }" + + register "tcc_offset" = "20" # TCC of 85C + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + # Default DPTF Policy for all drawcia boards if not overridden + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""5V regulator"" + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 80, 1000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 4000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 51, 1000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 60, 1000) + }" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 119, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 115, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 115, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 115, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 115, SHUTDOWN) + }" + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3800, + .max_power = 5800, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + device generic 0 alias dptf_policy on end + end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on |