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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 13:52:11 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2023-01-30 10:49:11 +0000 |
| commit | 69cd729c0cde6f15d1de692f5a2da5d3dfe8ba15 (patch) | |
| tree | 4f21a3de147f422336545ed3164581b6b80c45d7 | |
| parent | 0a97e466163dda4e55c1eda145646054dcd8dd06 (diff) | |
| download | coreboot-69cd729c0cde6f15d1de692f5a2da5d3dfe8ba15.tar.gz coreboot-69cd729c0cde6f15d1de692f5a2da5d3dfe8ba15.tar.bz2 coreboot-69cd729c0cde6f15d1de692f5a2da5d3dfe8ba15.zip | |
mb/*: Remove lapic from devicetree
The parallel mp code picks up lapics at runtime, so remove it from all
devicetrees that use this codebase.
Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
111 files changed, 108 insertions, 358 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index ab8787c32cdc..cc59992176fb 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -100,9 +100,7 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 84eb3cf81887..38a56cad7757 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -32,9 +32,7 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1025 0x1037 inherit device ref system_agent on diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index a45127c0b33f..9bffafdb76e9 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -41,9 +41,7 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on # Host Bridge subsystemid 0x1849 0x191f diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb index 7ee69e41a28d..a6505529154c 100644 --- a/src/mainboard/asus/p2b/devicetree.cb +++ b/src/mainboard/asus/p2b/devicetree.cb @@ -1,9 +1,5 @@ chip northbridge/intel/i440bx # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC - end - end + device cpu_cluster 0 on end # APIC cluster device domain 0 on # PCI domain device pci 0.0 on end # Host bridge device pci 1.0 on end # PCI/AGP bridge diff --git a/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb index ce36ce60d033..ed6224fbd7c1 100644 --- a/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb @@ -1,11 +1,5 @@ chip northbridge/intel/i440bx # Northbridge device cpu_cluster 0 on # (L)APIC cluster - chip cpu/intel/slot_1 # CPU socket 0 - device lapic 0 on end # Local APIC of CPU 0 - end - chip cpu/intel/slot_1 # CPU socket 1 - device lapic 1 on end # Local APIC of CPU 1 - end end device domain 0 on # PCI domain chip southbridge/intel/i82371eb # Southbridge diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb index b261a3514f96..adcce28057e7 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb @@ -1,11 +1,5 @@ chip northbridge/intel/i440bx # Northbridge device cpu_cluster 0 on # (L)APIC cluster - chip cpu/intel/slot_1 # CPU socket 0 - device lapic 0 on end # Local APIC of CPU 0 - end - chip cpu/intel/slot_1 # CPU socket 1 - device lapic 1 on end # Local APIC of CPU 1 - end end device domain 0 on # PCI domain chip southbridge/intel/i82371eb # Southbridge diff --git a/src/mainboard/bostentech/gbyt4/devicetree.cb b/src/mainboard/bostentech/gbyt4/devicetree.cb index 15a5d861dae2..f115303944f9 100644 --- a/src/mainboard/bostentech/gbyt4/devicetree.cb +++ b/src/mainboard/bostentech/gbyt4/devicetree.cb @@ -29,9 +29,7 @@ chip soc/intel/baytrail # Disable SLP_X stretching after SUS power well fail. register "disable_slp_x_stretch_sus_fail" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # SoC router device pci 02.0 on end # GFX diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index ce683b37dc9f..a98d144147dc 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -55,9 +55,7 @@ chip soc/intel/cannonlake register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1558 0x1401 inherit diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index d22f57419afc..765d17c471ad 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -35,9 +35,7 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1558 0x1313 inherit device ref system_agent on end diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb index e194ba647317..73f32e3a5d37 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb @@ -2,7 +2,6 @@ chip soc/intel/tigerlake device cpu_cluster 0 on register "tcc_offset" = "12" register "eist_enable" = "true" - device lapic 0 on end end device domain 0 on subsystemid 0x1558 0x14a1 inherit diff --git a/src/mainboard/emulation/qemu-i440fx/devicetree.cb b/src/mainboard/emulation/qemu-i440fx/devicetree.cb index a4fcef1fd91e..385fa247b2c3 100644 --- a/src/mainboard/emulation/qemu-i440fx/devicetree.cb +++ b/src/mainboard/emulation/qemu-i440fx/devicetree.cb @@ -1,9 +1,5 @@ chip mainboard/emulation/qemu-i440fx - device cpu_cluster 0 on - chip cpu/qemu-x86 - device lapic 0 on end - end - end + device cpu_cluster 0 on end device domain 0 on device pci 0.0 on end # northbridge (i440fx) chip southbridge/intel/i82371eb # southbridge diff --git a/src/mainboard/emulation/qemu-q35/devicetree.cb b/src/mainboard/emulation/qemu-q35/devicetree.cb index ff0589fa6052..6bd3d9dc322f 100644 --- a/src/mainboard/emulation/qemu-q35/devicetree.cb +++ b/src/mainboard/emulation/qemu-q35/devicetree.cb @@ -1,9 +1,5 @@ chip mainboard/emulation/qemu-q35 - device cpu_cluster 0 on - chip cpu/qemu-x86 - device lapic 0 on end - end - end + device cpu_cluster 0 on end device domain 0 on device pci 0.0 mandatory end # northbridge (q35) chip southbridge/intel/i82801ix diff --git a/src/mainboard/facebook/fbg1701/devicetree.cb b/src/mainboard/facebook/fbg1701/devicetree.cb index a340fdc37c4e..a77a6405f721 100644 --- a/src/mainboard/facebook/fbg1701/devicetree.cb +++ b/src/mainboard/facebook/fbg1701/devicetree.cb @@ -82,9 +82,7 @@ chip soc/intel/braswell # CPLD requires continuous mode register "serirq_mode" = "SERIRQ_CONTINUOUS" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # 8086 2280 - SoC router diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 05bcc122577c..a4a090674e2c 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -212,9 +212,7 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index 828f5bb2d265..b81583582031 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -5,11 +5,7 @@ chip northbridge/intel/pineview # Northbridge register "use_crt" = "true" register "use_lvds" = "false" - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_FCBGA559 # CPU - device lapic 0 on end # APIC - end - end + device cpu_cluster 0 on end # APIC cluster device domain 0 on # PCI domain subsystemid 0x105b 0x0d55 inherit device pci 0.0 on end # Host Bridge diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 5064cd942817..576be3497359 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -2,11 +2,7 @@ chip northbridge/intel/i945 - device cpu_cluster 0 on - ops i945_cpu_bus_ops - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end + device cpu_cluster 0 on ops i945_cpu_bus_ops end register "pci_mmio_size" = "768" diff --git a/src/mainboard/gigabyte/ga-d510ud/devicetree.cb b/src/mainboard/gigabyte/ga-d510ud/devicetree.cb index 18f96c64a01f..891594a8936d 100644 --- a/src/mainboard/gigabyte/ga-d510ud/devicetree.cb +++ b/src/mainboard/gigabyte/ga-d510ud/devicetree.cb @@ -3,11 +3,7 @@ chip northbridge/intel/pineview register "use_crt" = "true" - device cpu_cluster 0 on - chip cpu/intel/socket_FCBGA559 - device lapic 0 on end - end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x105b 0x0d55 inherit device pci 0.0 on end # Host Bridge diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index c968dfc0b766..c987d3b58391 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -91,9 +91,7 @@ chip soc/intel/braswell # Allow PCIe devices to wake system from suspend register "pcie_wake_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on # EDS Table 24-4, Figure 24-5 device pci 00.0 on end # 8086 2280 - SoC transaction router diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d819ca7ee83a..7f55eaf36f5a 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -216,9 +216,7 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 1e9ffd9255e8..3a7886992096 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -228,9 +228,7 @@ chip soc/intel/skylake }" register "tcc_offset" = "10" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 5ecc77bc7794..95d5368f529b 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -305,9 +305,7 @@ chip soc/intel/skylake }" register "tcc_offset" = "6" # TCC of 94C - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 9a3e61949952..f7c181944adc 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -81,9 +81,7 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 976d82970c8f..1af96c586a63 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -195,9 +195,7 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index abf53b47c53b..eec90bcd0d97 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index a801e2b10e1b..4c759f6d047a 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -227,9 +227,7 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index b209fcdd7f12..d963d9df1f1f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -249,9 +249,7 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_E15" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 2b1a19021c96..aa905d105b21 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -264,9 +264,7 @@ chip soc/intel/skylake .psys_pmax = 101, }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index e8c735d30c6e..25f75b8ffd23 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -271,9 +271,7 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_E15" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index a193e6a52bfb..b381a253a536 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -244,9 +244,7 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index beb78c65d9f8..66c07db41f71 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -230,9 +230,7 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_E15" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index bcfb2668526d..7cc3eb3029b4 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -250,9 +250,7 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_E15" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 976d82970c8f..1af96c586a63 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -195,9 +195,7 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 1ebf1e8e3d27..532680b0ef72 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -53,9 +53,7 @@ chip soc/intel/baytrail # Disable SLP_X stretching after SUS power well fail. register "disable_slp_x_stretch_sus_fail" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # SoC router device pci 02.0 on end # GFX diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index ddb78a54fd2b..2199ac091229 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index d14033065caa..70524972b114 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index ee1e0f3d8742..bf404647e15c 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index de2e920f4af1..1ee9c3849c80 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 197c911226f9..7c775ef5bc35 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 86b961d93360..ee7fa60ee85e 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -208,9 +208,7 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "MISCCFG_GPIO_PM_CONFIG_BITS" register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 903bcc6d4321..f01950eff04d 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -213,9 +213,7 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "MISCCFG_GPIO_PM_CONFIG_BITS" register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/google/smaug/devicetree.cb b/src/mainboard/google/smaug/devicetree.cb index 247085cd8451..18cb1be9e205 100644 --- a/src/mainboard/google/smaug/devicetree.cb +++ b/src/mainboard/google/smaug/devicetree.cb @@ -1,8 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only chip soc/nvidia/tegra210 - device cpu_cluster 0 on - end + device cpu_cluster 0 on end register "display_controller" = "TEGRA_ARM_DISPLAYA" register "xres" = "2560" diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 5dc62aafc882..4a575f89618a 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -7,9 +7,7 @@ chip soc/intel/skylake register "eist_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x103c 0x2b5e inherit device pci 00.0 on end # Host bridge diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 4c5b0c61f672..70a8706803b1 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -6,9 +6,7 @@ fw_config end chip soc/intel/alderlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb index 5421dc32621e..ef361b0c8517 100644 --- a/src/mainboard/intel/apollolake_rvp/devicetree.cb +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -7,9 +7,7 @@ chip soc/intel/apollolake register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/intel/cedarisland_crb/devicetree.cb b/src/mainboard/intel/cedarisland_crb/devicetree.cb index e89008211189..ea8b4e65766d 100644 --- a/src/mainboard/intel/cedarisland_crb/devicetree.cb +++ b/src/mainboard/intel/cedarisland_crb/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/xeon_sp/cpx - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host bridge device pci 04.0 on end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index e0ea3f20fa6c..051eba023cc9 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # FSP configuration register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb index a1455848e977..2269d740ed37 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # FSP configuration register "RMT" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index af5fc2de94ec..b6bf5a885258 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # FSP configuration register "RMT" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index f20622c9df7f..ce46c637eaca 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index 55b340caf35d..b9fe4236e2b7 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # Enable eDP device register "DdiPortEdp" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb index dc8874afe624..9c080230e010 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -1,8 +1,6 @@ chip soc/intel/cannonlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # Enable eDP device register "DdiPortEdp" = "1" diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index 0464b7489f56..82735c655667 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -5,11 +5,7 @@ chip northbridge/intel/pineview # Northbridge register "use_crt" = "true" register "use_lvds" = "false" - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_FCBGA559 # CPU - device lapic 0 on end # APIC - end - end + device cpu_cluster 0 on end # APIC cluster device domain 0 on # PCI domain device pci 0.0 on end # Host Bridge device pci 2.0 on end # Integrated graphics controller diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index d3d114232d80..2c952bf9c14b 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 6ab391e36b52..45fb7361ba2f 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index bae6198118a5..bf1b2359143b 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -109,9 +109,7 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 3fffc4a80ef6..5c5382fbaaf1 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -150,9 +150,7 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_G5" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index deb9f38c7a72..bc068c6d696d 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -157,9 +157,7 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_A7" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb index 76362e663e2b..add83fe4377b 100644 --- a/src/mainboard/intel/leafhill/devicetree.cb +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -7,9 +7,7 @@ chip soc/intel/apollolake register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb index 76362e663e2b..add83fe4377b 100644 --- a/src/mainboard/intel/minnow3/devicetree.cb +++ b/src/mainboard/intel/minnow3/devicetree.cb @@ -7,9 +7,7 @@ chip soc/intel/apollolake register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 7cf13ec9642e..fcd99ac610ce 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -192,9 +192,7 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration #register "sdcard_cd_gpio" = "GPP_A7" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 8d800950192d..932a5c755db9 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/alderlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 848b0c31c53d..d44a1b64ab6f 100644 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -80,9 +80,7 @@ chip soc/intel/braswell # Allow PCIe devices to wake system from suspend register "pcie_wake_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on # EDS Table 24-4, Figure 24-5 device pci 00.0 on end # 8086 2280 - SoC transaction router diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index 002f07ef40f1..46bfd95af574 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -63,9 +63,7 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb index 9248c0c21cea..e77a1727673d 100644 --- a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb @@ -2,9 +2,7 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # Override USB port configuration register "usb_config_override" = "1" diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb index 20089df1b619..7ce2480d55d3 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb +++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb @@ -5,9 +5,7 @@ chip soc/intel/apollolake register "enable_vtd" = "1" register "dptf_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 00.1 on end # DPTF diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 39c2e33a282d..26feab441c3a 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -152,9 +152,7 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index f6b3c8bc1f8b..7d5839ed1d2f 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -48,9 +48,7 @@ chip soc/intel/xeon_sp/cpx register "cstate_states" = "CSTATES_C1C6" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device gpio 0 alias pch_gpio on end diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 1f7c9eba229b..fbf066276b5d 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -40,9 +40,7 @@ chip soc/intel/xeon_sp/skx register "gen2_dec" = "0x000c0ca1" # IPMI KCS - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device gpio 0 alias pch_gpio on end diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 243a9ba5cae5..1abcd61ff5b6 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -1,11 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00730F01 - device lapic 0 on end - end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1022 0x1410 inherit diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 8273a9604c13..99353f46368b 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -1,11 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00730F01 - device lapic 0 on end - end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1022 0x1410 inherit diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index f399d8bef11a..c4975cc6d804 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -1,11 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00730F01 - device lapic 0 on end - end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1022 0x1410 inherit diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index c69401be1e22..0aee11c652c9 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -1,11 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00730F01 - device lapic 0 on end - end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1022 0x1410 inherit diff --git a/src/mainboard/portwell/m107/devicetree.cb b/src/mainboard/portwell/m107/devicetree.cb index d77967264fb3..3bc67372f564 100644 --- a/src/mainboard/portwell/m107/devicetree.cb +++ b/src/mainboard/portwell/m107/devicetree.cb @@ -79,9 +79,7 @@ chip soc/intel/braswell # Allow PCIe devices to wake system from suspend register "pcie_wake_enable" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # 8086 2280 - SoC router diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 70ff564b1e44..8c2dbda38e7f 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -136,9 +136,7 @@ chip soc/intel/cannonlake register "DisableHeciRetry" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/protectli/vault_bsw/devicetree.cb b/src/mainboard/protectli/vault_bsw/devicetree.cb index 4b750c00f021..02a1642092f6 100644 --- a/src/mainboard/protectli/vault_bsw/devicetree.cb +++ b/src/mainboard/protectli/vault_bsw/devicetree.cb @@ -79,9 +79,7 @@ chip soc/intel/braswell # Enable SERIRQ continuous register "serirq_mode" = "SERIRQ_CONTINUOUS" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # 8086 2280 - SoC transaction router device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping GFX diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index feb8b9f1e3a0..4e4cbac04a4f 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -189,9 +189,7 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb index a1fc9e11c548..ff21977e07fe 100644 --- a/src/mainboard/purism/librem_cnl/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/devicetree.cb @@ -41,9 +41,7 @@ chip soc/intel/cannonlake register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 94b79f9bc9c9..4f4b36fa1d0e 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -149,9 +149,7 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index b2cb3603158b..1365d85126ca 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -166,9 +166,7 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/scaleway/tagada/devicetree.cb b/src/mainboard/scaleway/tagada/devicetree.cb index e9932a3153a6..4de8bb5d80dd 100644 --- a/src/mainboard/scaleway/tagada/devicetree.cb +++ b/src/mainboard/scaleway/tagada/devicetree.cb @@ -31,9 +31,7 @@ chip soc/intel/denverton_ns register "ipc2" = "0x00000000" # IPC2 register "ipc3" = "0x00000000" # IPC3 - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 81dae2ea1fd3..8d6c589e4a78 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -7,9 +7,7 @@ chip soc/intel/cannonlake register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index b4d99700cae8..cee1967a36ea 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -7,9 +7,7 @@ chip soc/intel/cannonlake register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index bb978f4dfee6..dad319e9ff99 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "sci_irq" = "SCIS_IRQ10" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index f1594d2b7748..b728438ed862 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "sci_irq" = "SCIS_IRQ10" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index e6e14cb16a0e..4fae59e38f96 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "sci_irq" = "SCIS_IRQ10" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index f997d08433a6..586d65e43430 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "sci_irq" = "SCIS_IRQ10" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index e2d2606a84da..40739df913f5 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "sci_irq" = "SCIS_IRQ10" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index 27b3b93b6ed4..c48eb5a030c4 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "sci_irq" = "SCIS_IRQ10" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb index b3775bd7a65b..ce716a0c8341 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end register "sci_irq" = "SCIS_IRQ10" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index e67004eff654..4e2fffc5443b 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index c922e9e988f1..758c8b174634 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb index 722162d2942f..9810a906141f 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/elkhartlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index abb63331843c..709d8e18b446 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # Graphics # TODO: diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index 72e6de20a88d..96011ea2c67c 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # Graphics # TODO: diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index e38909653241..ed1d48ea67d9 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -38,9 +38,7 @@ chip soc/intel/alderlake register "pmc_gpe0_dw2" = "GPP_E" # Device Tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device ref igpu on diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index a1def8d3f500..9a71015ae71f 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -50,9 +50,7 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" # Actual device tree. - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index f67106f15c99..edc8a1650358 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -49,9 +49,7 @@ chip soc/intel/skylake LPC_IOE_EC_62_66" # Actual device tree. - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device ref igpu on end diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index c2728dc266bd..cd8c48071a0b 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -64,9 +64,7 @@ chip soc/intel/tigerlake register "PcieClkSrcClkReq[6]" = "PCIE_CLK_NOTUSED" # Actual device tree. - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device ref igpu on end diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 6f627bb40250..b4a08bf4182e 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -26,9 +26,7 @@ chip soc/intel/skylake register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 01.0 off end # CPU PCIe Port 10 (x16) diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 4f16bbd46eaf..94f1bdda60c0 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -47,9 +47,7 @@ chip soc/intel/cannonlake register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1558 0x65d1 inherit diff --git a/src/mainboard/system76/adl-p/devicetree.cb b/src/mainboard/system76/adl-p/devicetree.cb index c7085b448b79..8f668bee3318 100644 --- a/src/mainboard/system76/adl-p/devicetree.cb +++ b/src/mainboard/system76/adl-p/devicetree.cb @@ -19,9 +19,7 @@ chip soc/intel/alderlake # Thermal register "tcc_offset" = "8" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device ref system_agent on end diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index b46dac026c12..59a1c14cead6 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -50,9 +50,7 @@ chip soc/intel/cannonlake register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1558 0x7714 inherit diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index 86e7aa4e67f3..90c5b719b00d 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -54,9 +54,7 @@ chip soc/intel/cannonlake register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index c02a6ec08600..d25b18a43e13 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -47,9 +47,7 @@ chip soc/intel/cannonlake register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 6322394ac1df..bcd1130f915f 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -103,9 +103,7 @@ chip soc/intel/skylake .dc_loadline = 310, }" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device ref system_agent on end diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index bb756166a105..733d02097902 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -54,9 +54,7 @@ chip soc/intel/cannonlake register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x1558 0x95e6 inherit diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index 7350dcd8bbe0..a05b5bd9e67a 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -52,9 +52,7 @@ chip soc/intel/cannonlake register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb index bce5c5d9278d..8e70572c6abe 100644 --- a/src/mainboard/system76/tgl-h/devicetree.cb +++ b/src/mainboard/system76/tgl-h/devicetree.cb @@ -78,9 +78,7 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw2" = "PMC_GPP_D" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on #From CPU EDS(575683) diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb index 0666a1a67c43..cdd9c048c903 100644 --- a/src/mainboard/system76/tgl-u/devicetree.cb +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -66,9 +66,7 @@ chip soc/intel/tigerlake register "CnviBtCore" = "true" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device ref system_agent on end diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 63a9016b1332..b15385538586 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -54,9 +54,7 @@ chip soc/intel/cannonlake register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index 128c1bba4544..867f3a5180e4 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -20,9 +20,7 @@ chip soc/intel/apollolake # 0:HS400 (Default) 1:HS200 2:DDR50 register "emmc_host_max_speed" = "1" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on subsystemid 0x8086 0x7270 inherit device pci 00.0 on end # - Host Bridge |