diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-02-18 11:10:34 -0700 |
|---|---|---|
| committer | Marc Jones <marc@marcjonesconsulting.com> | 2017-05-02 05:16:38 +0200 |
| commit | 6a7ebd4e08b234bdf79e6ffbde8ff2a7a0e57fb7 (patch) | |
| tree | f7796ea3c3d908c80f52824bc45fa83f81dbf63a | |
| parent | d0e465456eedd7d39442a82fe3b2186784a9ff60 (diff) | |
| download | coreboot-6a7ebd4e08b234bdf79e6ffbde8ff2a7a0e57fb7.tar.gz coreboot-6a7ebd4e08b234bdf79e6ffbde8ff2a7a0e57fb7.tar.bz2 coreboot-6a7ebd4e08b234bdf79e6ffbde8ff2a7a0e57fb7.zip | |
amd/pi/00670F00: Reserve A0000-FFFFF
Claim memory-mapped regions in the legacy area.
Claim an MMIO resource for the A000 and B000 segments, and reserved
resource for C000 through F000 segments.
These changes allow code and information to be retained in the event
unused regions get wiped.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit d612d4fe69881609d42053496409c452e1014947)
Change-Id: I9c47c919bbfd0edccf752e052f32d1e47c1a1324
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19156
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
| -rw-r--r-- | src/northbridge/amd/pi/00670F00/northbridge.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index c21d030056d8..3ba0687df1d2 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -850,6 +850,14 @@ static void domain_set_resources(device_t dev) assign_resources(link); } } + /* + * Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xfffff: RAM + */ + mmio_resource(dev, 0xa0000, 0xa0000 / KiB, 0x20000 / KiB); + reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB); } static struct device_operations pci_domain_ops = { |