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authorMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-11-13 20:57:12 -0600
committerFelix Held <felix-coreboot@felixheld.de>2023-12-06 19:12:59 +0000
commit6bb0f8aaa489e5f8da2818069623bc2f202a42ef (patch)
tree1e93f565afee3de2987481b61b2afbd13ea06ee6
parentfca7fd2a7367f27f45d9b784719f984a1128b758 (diff)
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soc/amd/common: Move PCIe CLKREQ programming under fsp
CLKREQ programming as currently implemented is completely dependent on FSP DXIO descriptors, so move under common/fsp/pci and rename the Kconfig to reflect the move. TEST=build google/{guybrush, skyrim, myst} Change-Id: I87b53d092ddc367b134c25949f9da7670a6a1d88 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin L Roth <gaumless@gmail.com>
-rw-r--r--src/soc/amd/cezanne/Kconfig2
-rw-r--r--src/soc/amd/common/block/pci/Kconfig7
-rw-r--r--src/soc/amd/common/block/pci/Makefile.inc1
-rw-r--r--src/soc/amd/common/fsp/pci/Kconfig7
-rw-r--r--src/soc/amd/common/fsp/pci/Makefile.inc5
-rw-r--r--src/soc/amd/common/fsp/pci/pcie_clk_req.c (renamed from src/soc/amd/common/block/pci/pcie_clk_req.c)0
-rw-r--r--src/soc/amd/mendocino/Kconfig2
-rw-r--r--src/soc/amd/phoenix/Kconfig2
8 files changed, 12 insertions, 14 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 3700f187720a..9c15dd98945d 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -55,7 +55,6 @@ config SOC_AMD_CEZANNE
select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
- select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
select SOC_AMD_COMMON_BLOCK_PM
select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
select SOC_AMD_COMMON_BLOCK_PSP_GEN2
@@ -74,6 +73,7 @@ config SOC_AMD_CEZANNE
select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
select SOC_AMD_COMMON_FSP_DMI_TABLES
select SOC_AMD_COMMON_FSP_PCI
+ select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
select SOC_AMD_COMMON_BLOCK_XHCI
select SSE2
diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig
index 1c21833bd226..302a6b84977b 100644
--- a/src/soc/amd/common/block/pci/Kconfig
+++ b/src/soc/amd/common/block/pci/Kconfig
@@ -16,10 +16,3 @@ config SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
depends on SOC_AMD_COMMON_BLOCK_PCI
help
Select this option to use AMD common PCIe GPP driver.
-
-config SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
- bool
- depends on SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
- help
- This option includes code to disable PCIe clock request if the corresponding
- PCIe device is disabled.
diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc
index 372c6ce41124..ece43cb67e93 100644
--- a/src/soc/amd/common/block/pci/Makefile.inc
+++ b/src/soc/amd/common/block/pci/Makefile.inc
@@ -5,7 +5,6 @@ ramstage-y += amd_pci_util.c
ramstage-y += pci_routing_info.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_prt.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER) += pcie_gpp.c
-ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ) += pcie_clk_req.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI
diff --git a/src/soc/amd/common/fsp/pci/Kconfig b/src/soc/amd/common/fsp/pci/Kconfig
index 9d6596cc8927..dce2c66562c8 100644
--- a/src/soc/amd/common/fsp/pci/Kconfig
+++ b/src/soc/amd/common/fsp/pci/Kconfig
@@ -3,3 +3,10 @@ config SOC_AMD_COMMON_FSP_PCI
select SOC_AMD_COMMON_BLOCK_PCI
help
This option enabled FSP to provide common PCI functions.
+
+config SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
+ bool
+ depends on SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
+ help
+ This option includes code to disable PCIe clock request if the corresponding
+ PCIe device is disabled.
diff --git a/src/soc/amd/common/fsp/pci/Makefile.inc b/src/soc/amd/common/fsp/pci/Makefile.inc
index 85418f395f6c..e0b2cd97a7ea 100644
--- a/src/soc/amd/common/fsp/pci/Makefile.inc
+++ b/src/soc/amd/common/fsp/pci/Makefile.inc
@@ -1,6 +1,5 @@
## SPDX-License-Identifier: GPL-2.0-only
-ifeq ($(CONFIG_SOC_AMD_COMMON_FSP_PCI),y)
-ramstage-y += pci_routing_info.c
+ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PCI) += pci_routing_info.c
-endif # CONFIG_SOC_AMD_COMMON_FSP_PCI
+ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PCIE_CLK_REQ) += pcie_clk_req.c
diff --git a/src/soc/amd/common/block/pci/pcie_clk_req.c b/src/soc/amd/common/fsp/pci/pcie_clk_req.c
index 881c650ed4b3..881c650ed4b3 100644
--- a/src/soc/amd/common/block/pci/pcie_clk_req.c
+++ b/src/soc/amd/common/fsp/pci/pcie_clk_req.c
diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig
index ef722804b7f1..d5aae5203b36 100644
--- a/src/soc/amd/mendocino/Kconfig
+++ b/src/soc/amd/mendocino/Kconfig
@@ -61,7 +61,6 @@ config SOC_AMD_REMBRANDT_BASE
select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
- select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
select SOC_AMD_COMMON_BLOCK_PM
select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
select SOC_AMD_COMMON_BLOCK_PSP_GEN2
@@ -82,6 +81,7 @@ config SOC_AMD_REMBRANDT_BASE
select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
select SOC_AMD_COMMON_FSP_DMI_TABLES
select SOC_AMD_COMMON_FSP_PCI
+ select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
select SSE2
select UDK_2017_BINDING
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index 9137bc5ce75d..d35ecc2a0077 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -60,7 +60,6 @@ config SOC_AMD_PHOENIX
select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
- select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
select SOC_AMD_COMMON_BLOCK_PM
select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct
@@ -80,6 +79,7 @@ config SOC_AMD_PHOENIX
select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
select SOC_AMD_COMMON_FSP_DMI_TABLES
select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct
+ select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
select SSE2
select UDK_2017_BINDING