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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-07-01 09:03:51 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-09-10 21:58:08 +0000
commit6c6eb652d5e26831adbba5e39467a5f1f383e802 (patch)
treea31a4a9573fd7965b922110a2d2fb8b5216da622
parent46c5f8f1d6d8ba4d3ea292a17b6bab025d543c22 (diff)
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soc/intel/common: Add Intel Power Engine support to discoverable PMC
In order to get rid of pep.asl, skylake also needs to support runtime generation of the Intel Power Engine, therefore add this support to devices that have a discoverable PMC as well. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4bf0c4a338301b335fa78617e0f2ed5a9f4360ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/soc/intel/common/block/pmc/pmc.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index 3d5f41dc5160..560ab9b2d85b 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -5,6 +5,7 @@
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <intelblocks/acpi.h>
#include <intelblocks/pmc.h>
#include <soc/pci_devs.h>
@@ -73,6 +74,12 @@ static void pch_pmc_read_resources(struct device *dev)
pch_pmc_add_io_resources(dev, config);
}
+static void pmc_fill_ssdt(const struct device *dev)
+{
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP))
+ generate_acpi_power_engine();
+}
+
static struct device_operations device_ops = {
.read_resources = pch_pmc_read_resources,
.set_resources = pci_dev_set_resources,
@@ -80,6 +87,9 @@ static struct device_operations device_ops = {
.init = pmc_soc_init,
.ops_pci = &pci_dev_ops_pci,
.scan_bus = scan_static_bus,
+#if CONFIG(HAVE_ACPI_TABLES)
+ .acpi_fill_ssdt = pmc_fill_ssdt,
+#endif
};
static const unsigned short pci_device_ids[] = {