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| author | Patrick Georgi <patrick.georgi@secunet.com> | 2011-03-01 07:26:00 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2011-03-01 07:26:00 +0000 |
| commit | 6eb6a7c8d57969cde6db50072ac4e1a241f6ade7 (patch) | |
| tree | 68d6a6fc77058c44b77e4a0cd7b51c0c24815935 | |
| parent | fb2d29ec75667eeccc793bcd786207a38b1cc1a7 (diff) | |
| download | coreboot-6eb6a7c8d57969cde6db50072ac4e1a241f6ade7.tar.gz coreboot-6eb6a7c8d57969cde6db50072ac4e1a241f6ade7.tar.bz2 coreboot-6eb6a7c8d57969cde6db50072ac4e1a241f6ade7.zip | |
libpayload: Add more libpci-compatibility (#defines)
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | payloads/libpayload/include/pci.h | 2 | ||||
| -rw-r--r-- | payloads/libpayload/include/pci/pci.h | 26 |
2 files changed, 28 insertions, 0 deletions
diff --git a/payloads/libpayload/include/pci.h b/payloads/libpayload/include/pci.h index 2490f6cb4cc2..005634a75048 100644 --- a/payloads/libpayload/include/pci.h +++ b/payloads/libpayload/include/pci.h @@ -42,6 +42,8 @@ typedef u32 pcidev_t; #define REG_SUBSYS_VENDOR_ID 0x2C #define REG_SUBSYS_ID 0x2E +#define REG_COMMAND_IO (1 << 0) +#define REG_COMMAND_MEM (1 << 1) #define REG_COMMAND_BM (1 << 2) #define HEADER_TYPE_NORMAL 0 diff --git a/payloads/libpayload/include/pci/pci.h b/payloads/libpayload/include/pci/pci.h index 9c7ced8621bc..53da0e175602 100644 --- a/payloads/libpayload/include/pci/pci.h +++ b/payloads/libpayload/include/pci/pci.h @@ -39,6 +39,32 @@ #define PCI_SUBSYSTEM_VENDOR_ID REG_SUBSYS_VENDOR_ID
#define PCI_SUBSYSTEM_ID REG_SUBSYS_ID
+#define PCI_COMMAND REG_COMMAND
+#define PCI_COMMAND_IO REG_COMMAND_IO
+#define PCI_COMMAND_MEMORY REG_COMMAND_MEM
+#define PCI_COMMAND_MASTER REG_COMMAND_BM
+
+#define PCI_HEADER_TYPE REG_HEADER_TYPE
+#define PCI_HEADER_TYPE_NORMAL HEADER_TYPE_NORMAL
+#define PCI_HEADER_TYPE_BRIDGE HEADER_TYPE_BRIDGE
+#define PCI_HEADER_TYPE_CARDBUS HEADER_TYPE_CARDBUS
+
+#define PCI_BASE_ADDRESS_0 0x10
+#define PCI_BASE_ADDRESS_1 0x14
+#define PCI_BASE_ADDRESS_2 0x18
+#define PCI_BASE_ADDRESS_3 0x1c
+#define PCI_BASE_ADDRESS_4 0x20
+#define PCI_BASE_ADDRESS_5 0x24
+#define PCI_BASE_ADDRESS_SPACE 1 // mask
+#define PCI_BASE_ADDRESS_SPACE_IO 1
+#define PCI_BASE_ADDRESS_SPACE_MEM 0
+#define PCI_BASE_ADDRESS_IO_MASK ~0xf
+#define PCI_BASE_ADDRESS_MEM_MASK ~0x3
+
+#define PCI_ROM_ADDRESS 0x30
+#define PCI_ROM_ADDRESS1 0x38 // on bridges
+#define PCI_ROM_ADDRESS_MASK ~0x7ff
+
struct pci_dev {
u16 domain;
u8 bus, dev, func;
|