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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2022-09-12 10:45:45 -0600 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-09-20 07:58:10 +0000 |
| commit | 7125318ac454b5e60cfadbe375ce6b8e97706b20 (patch) | |
| tree | 3a831b7e4b2918a6ff81fb1f7bb305027716eb04 | |
| parent | 61e5816b26e62f4b53d82bb8f3d1c17a3d202610 (diff) | |
| download | coreboot-7125318ac454b5e60cfadbe375ce6b8e97706b20.tar.gz coreboot-7125318ac454b5e60cfadbe375ce6b8e97706b20.tar.bz2 coreboot-7125318ac454b5e60cfadbe375ce6b8e97706b20.zip | |
mb/google/dedede/var/boten: Turn off camera during S0ix
Add a variant specific S0ix hook to fill the SSDT table to disable and
enable camera during suspend and resume respectively.
BUG=b:206911455
TEST=Build Boten BIOS image. Ensure that camera is disabled during
suspend and enabled during resume.
Change-Id: I3229b22b8d8651bf2d9df25b10ce6749efde7cf6
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
| -rw-r--r-- | src/mainboard/google/dedede/variants/boten/variant.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/boten/variant.c b/src/mainboard/google/dedede/variants/boten/variant.c index 432c9501902e..8d60bf5ce54d 100644 --- a/src/mainboard/google/dedede/variants/boten/variant.c +++ b/src/mainboard/google/dedede/variants/boten/variant.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpi.h> +#include <acpi/acpigen.h> #include <baseboard/variants.h> #include <delay.h> #include <ec/google/chromeec/ec.h> @@ -46,3 +47,11 @@ const char *get_wifi_sar_cbfs_filename(void) return WIFI_SAR_CBFS_DEFAULT_FILENAME; } + +void variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + if (entry == S0IX_ENTRY) + acpigen_soc_clear_tx_gpio(GPP_D13); + else if (entry == S0IX_EXIT) + acpigen_soc_set_tx_gpio(GPP_D13); +} |