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| author | Jes Klinke <jbk@google.com> | 2020-07-31 09:48:35 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2020-08-11 20:54:34 +0000 |
| commit | 739c50340431f34a8e4fbc0736ebb11e161fdf0f (patch) | |
| tree | b137b8d3fa20b787db3b59af8bf1b9a9a2ed576e | |
| parent | 89ed7900287f3f38134aead3647eb153787604d1 (diff) | |
| download | coreboot-739c50340431f34a8e4fbc0736ebb11e161fdf0f.tar.gz coreboot-739c50340431f34a8e4fbc0736ebb11e161fdf0f.tar.bz2 coreboot-739c50340431f34a8e4fbc0736ebb11e161fdf0f.zip | |
soc/intel/common/block/gspi: Recalculate BAR after resource allocation
The base address of the memory mapped I/O registers should not
be cached across resource allocation. This CL will evict the cached
value upon exiting the BS_DEV_RESOURCES stage.
Change-Id: I81f2b5bfadbf1aaa3b38cca2bcc44ce521666821
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44084
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/common/block/gspi/gspi.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 599ab7e52c28..836371372a6f 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -2,6 +2,7 @@ #include <device/mmio.h> #include <assert.h> +#include <bootstate.h> #include <console/console.h> #include <delay.h> #include <device/device.h> @@ -257,6 +258,17 @@ static uintptr_t gspi_get_bus_base_addr(unsigned int gspi_bus) return gspi_base[gspi_bus]; } +/* + * PCI resource allocation will likely change the base address of the mapped + * I/O registers. Clearing the cached value after the allocation step will + * cause it to be recomputed by gspi_calc_base_addr() on next access. + */ +static void gspi_clear_cached_base(void *unused) +{ + memset(gspi_base, 0, sizeof(gspi_base)); +} +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, gspi_clear_cached_base, NULL); + /* Parameters for GSPI controller operation. */ struct gspi_ctrlr_params { uintptr_t mmio_base; |