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| author | Raul E Rangel <rrangel@chromium.org> | 2021-07-12 09:21:51 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-07-14 17:54:36 +0000 |
| commit | 73e0f18b35f154dc54994474448df283f51d659d (patch) | |
| tree | c1cf56b1e1097ac969176186bc8703f9c9ba01cc | |
| parent | 2c7080692a281d64a99aeb8db7b65b33b83c3f90 (diff) | |
| download | coreboot-73e0f18b35f154dc54994474448df283f51d659d.tar.gz coreboot-73e0f18b35f154dc54994474448df283f51d659d.tar.bz2 coreboot-73e0f18b35f154dc54994474448df283f51d659d.zip | |
soc/amd/cezanne: Move APOB update into ramstage
There is no technical reason this needs to be done in romstage. Moving
it into ramstage allow us (in future CLs) to use threads to pre-load
the apob from SPI.
BUG=b:179699789
TEST=Boot and Ezkinil and Guybrush and verify APOB update still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
| -rw-r--r-- | src/soc/amd/cezanne/romstage.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/block/apob/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/apob/apob_cache.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/apob_cache.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/romstage.c | 2 |
5 files changed, 4 insertions, 6 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index b64fb4bbe530..9e863c396653 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <amdblocks/acpimmio.h> -#include <amdblocks/apob_cache.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> #include <arch/cpu.h> @@ -25,7 +24,6 @@ asmlinkage void car_stage_entry(void) fill_chipset_state(); fsp_memory_init(acpi_is_wakeup_s3()); - soc_update_apob_cache(); /* Fixup settings FSP-M should not be changing */ fch_disable_legacy_dma_io(); diff --git a/src/soc/amd/common/block/apob/Makefile.inc b/src/soc/amd/common/block/apob/Makefile.inc index 16baf81813e6..6e217df64862 100644 --- a/src/soc/amd/common/block/apob/Makefile.inc +++ b/src/soc/amd/common/block/apob/Makefile.inc @@ -1,3 +1,4 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB),y) romstage-y += apob_cache.c +ramstage-y += apob_cache.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_APOB diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c index 34d54727fceb..c41627b7acef 100644 --- a/src/soc/amd/common/block/apob/apob_cache.c +++ b/src/soc/amd/common/block/apob/apob_cache.c @@ -4,6 +4,7 @@ #include <amdblocks/apob_cache.h> #include <assert.h> #include <boot_device.h> +#include <bootstate.h> #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> @@ -96,7 +97,7 @@ static void *get_apob_from_nv_region(struct region *region) } /* Save APOB buffer to flash */ -void soc_update_apob_cache(void) +static void soc_update_apob_cache(void *unused) { struct apob_base_header *apob_rom; struct region_device write_rdev; @@ -183,3 +184,4 @@ void *soc_fill_apob_cache(void) */ return get_apob_nv_address(); } +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, soc_update_apob_cache, NULL); diff --git a/src/soc/amd/common/block/include/amdblocks/apob_cache.h b/src/soc/amd/common/block/include/amdblocks/apob_cache.h index 1d29ddc279c6..79228e5de25e 100644 --- a/src/soc/amd/common/block/include/amdblocks/apob_cache.h +++ b/src/soc/amd/common/block/include/amdblocks/apob_cache.h @@ -4,6 +4,5 @@ #define AMD_BLOCK_APOB_CACHE_H void *soc_fill_apob_cache(void); -void soc_update_apob_cache(void); #endif /* AMD_BLOCK_APOB_CACHE_H */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index d3ceec587f02..197241084f1f 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <amdblocks/apob_cache.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> #include <arch/cpu.h> @@ -27,7 +26,6 @@ asmlinkage void car_stage_entry(void) post_code(0x43); fsp_memory_init(acpi_is_wakeup_s3()); - soc_update_apob_cache(); memmap_stash_early_dram_usage(); |