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| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2021-09-08 00:37:30 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-09 14:20:35 +0000 |
| commit | 7bbde76014a571cbe2344615f19b1e9bc905b84a (patch) | |
| tree | af97dd4cea8ad4282d5339fe6923dc2e3251ef48 | |
| parent | fd63e11f714eb1e908df2005d9becb492a5247e9 (diff) | |
| download | coreboot-7bbde76014a571cbe2344615f19b1e9bc905b84a.tar.gz coreboot-7bbde76014a571cbe2344615f19b1e9bc905b84a.tar.bz2 coreboot-7bbde76014a571cbe2344615f19b1e9bc905b84a.zip | |
soc/amd/common/block/include/i2c: introduce I2C_RESET_SCL_PIN macro
Add and use the I2C_RESET_SCL_PIN macro for populating the i2c_scl_pins
array that is used for the sb_reset_i2c_peripherals call to bring the
I2C buses into a defined state.
TEST=Timeless build results in identical image for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifedc09d0bf745545fa0510df7d5037f02b9012a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/soc/amd/cezanne/early_fch.c | 8 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/i2c.h | 7 | ||||
| -rw-r--r-- | src/soc/amd/picasso/early_fch.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/bootblock.c | 8 |
4 files changed, 17 insertions, 10 deletions
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index cdb871b91685..fdacb9f525e6 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -15,10 +15,10 @@ /* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ static const struct soc_i2c_scl_pin i2c_scl_pins[] = { - { PAD_GPO(I2C0_SCL_PIN, HIGH), GPIO_I2C0_SCL }, - { PAD_GPO(I2C1_SCL_PIN, HIGH), GPIO_I2C1_SCL }, - { PAD_GPO(I2C2_SCL_PIN, HIGH), GPIO_I2C2_SCL }, - { PAD_GPO(I2C3_SCL_PIN, HIGH), GPIO_I2C3_SCL }, + I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL), + I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL), + I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), + I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), }; static void reset_i2c_peripherals(void) diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h index 4a7a7e83a0f9..22a408ec92e5 100644 --- a/src/soc/amd/common/block/include/amdblocks/i2c.h +++ b/src/soc/amd/common/block/include/amdblocks/i2c.h @@ -35,6 +35,13 @@ struct soc_i2c_scl_pin { uint8_t pin_mask; }; +/* Macro to populate the elements of the array of soc_i2c_scl_pin in the SoC code */ +#define I2C_RESET_SCL_PIN(pin_name, pin_mask_value) \ +{ \ + .pin = PAD_CFG_STRUCT(pin_name, pin_name ## _IOMUX_GPIOxx, PAD_OUTPUT(HIGH)), \ + .pin_mask = pin_mask_value, \ +} + /** * Information about I2C peripherals that need to be reset. * @i2c_scl_reset_mask: Bit mask of I2C buses that need to be reset based on the device tree diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 048ce12819cb..ae3aed2d98d7 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -17,8 +17,8 @@ /* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ static const struct soc_i2c_scl_pin i2c_scl_pins[] = { - { PAD_GPO(I2C2_SCL_PIN, HIGH), GPIO_I2C2_SCL }, - { PAD_GPO(I2C3_SCL_PIN, HIGH), GPIO_I2C3_SCL }, + I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), + I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), /* I2C4 is a peripheral device only */ }; diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c index 499ff633d426..8c6fde521a4c 100644 --- a/src/soc/amd/stoneyridge/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -30,10 +30,10 @@ /* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ static const struct soc_i2c_scl_pin i2c_scl_pins[] = { - { PAD_GPO(I2C0_SCL_PIN, HIGH), GPIO_I2C0_SCL }, - { PAD_GPO(I2C1_SCL_PIN, HIGH), GPIO_I2C1_SCL }, - { PAD_GPO(I2C2_SCL_PIN, HIGH), GPIO_I2C2_SCL }, - { PAD_GPO(I2C3_SCL_PIN, HIGH), GPIO_I2C3_SCL }, + I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL), + I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL), + I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), + I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), }; /* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ |