cpu/x86/smm: Promote smm_memory_map()

Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

13 files changed, 49 insertions, 30 deletions

diff --git a/configs/config.intel_galileo_gen2.debug b/configs/config.intel_galileo_gen2.debug
index ceea7d0af77d..f4fdb2d7eb0f 100644
--- a/configs/config.intel_galileo_gen2.debug
+++ b/configs/config.intel_galileo_gen2.debug
@@ -3,7 +3,6 @@ CONFIG_VENDOR_INTEL=y
 CONFIG_BOARD_INTEL_GALILEO=y
 # CONFIG_FSP_DEBUG_ALL is not set
 CONFIG_DISPLAY_MTRRS=y
-CONFIG_DISPLAY_SMM_MEMORY_MAP=y
 CONFIG_DISPLAY_ESRAM_LAYOUT=y
 CONFIG_BOOTBLOCK_NORMAL=y
 CONFIG_ON_DEVICE_ROM_LOAD=y
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 624f3ff9b704..43fbe8af38e8 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -15,6 +15,7 @@
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <arch/symbols.h>
 #include <commonlib/helpers.h>
 #include <program_loading.h>
@@ -69,6 +70,9 @@ static void romstage_main(unsigned long bist)
 		printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
 	}
 
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
 	prepare_and_run_postcar(&early_mtrrs);
 	/* We do not return here. */
 }
diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c
index df9dea5c0fa7..07789f4ac1b3 100644
--- a/src/cpu/x86/smm/tseg_region.c
+++ b/src/cpu/x86/smm/tseg_region.c
@@ -84,3 +84,23 @@ void __weak stage_cache_external_region(void **base, size_t *size)
 		*size = 0;
 	}
 }
+
+void smm_list_regions(void)
+{
+	uintptr_t base;
+	size_t size;
+	int i;
+
+	smm_region(&base, &size);
+	if (!size)
+		return;
+
+	printk(BIOS_DEBUG, "SMM Memory Map\n");
+	printk(BIOS_DEBUG, "SMRAM       : 0x%zx 0x%zx\n", base, size);
+
+	for (i = 0; i < SMM_SUBREGION_NUM; i++) {
+		if (smm_subregion(i, &base, &size))
+			continue;
+		printk(BIOS_DEBUG, " Subregion %d: 0x%zx 0x%zx\n", i, base, size);
+	}
+}
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index 4b567da188b2..57068cf2e970 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -30,25 +30,6 @@ __weak void soc_after_silicon_init(void)
 {
 }
 
-/* Display SMM memory map */
-static void smm_memory_map(void)
-{
-	uintptr_t base;
-	size_t size;
-	int i;
-
-	printk(BIOS_SPEW, "SMM Memory Map\n");
-
-	smm_region(&base, &size);
-	printk(BIOS_SPEW, "SMRAM       : 0x%zx 0x%zx\n", base, size);
-
-	for (i = 0; i < SMM_SUBREGION_NUM; i++) {
-		if (smm_subregion(i, &base, &size))
-			continue;
-		printk(BIOS_SPEW, " Subregion %d: 0x%zx 0x%zx\n", i, base, size);
-	}
-}
-
 static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
 {
 	const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
@@ -147,9 +128,6 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
 
 static void fsp_cache_save(struct prog *fsp)
 {
-	if (CONFIG(DISPLAY_SMM_MEMORY_MAP))
-		smm_memory_map();
-
 	if (CONFIG(NO_STAGE_CACHE))
 		return;
 
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index c3387447d800..d8b9efeaa993 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -160,4 +160,7 @@ enum {
  * 0 on success, < 0 on failure. */
 int smm_subregion(int sub, uintptr_t *start, size_t *size);
 
+/* Print the SMM memory layout on console. */
+void smm_list_regions(void);
+
 #endif /* CPU_X86_SMM_H */
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig
index c3d846c68632..7e1742d0f98c 100644
--- a/src/mainboard/intel/galileo/Kconfig
+++ b/src/mainboard/intel/galileo/Kconfig
@@ -94,7 +94,6 @@ config FSP_DEBUG_ALL
 # Enable display and verification for coreboot build tests
 	select DISPLAY_HOBS
 	select DISPLAY_MTRRS
-	select DISPLAY_SMM_MEMORY_MAP
 	select DISPLAY_UPD_DATA
 	select DISPLAY_ESRAM_LAYOUT
 	select DISPLAY_FSP_CALLS_AND_STATUS
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index dae64cc4205c..22b5ce4be009 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -67,6 +67,9 @@ asmlinkage void car_stage_entry(void)
 	if (romstage_handoff_init(s3_resume))
 		printk(BIOS_ERR, "Failed to set romstage handoff data\n");
 
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
 	post_code(0x44);
 	if (postcar_frame_init(&pcf, 1 * KiB))
 		die("Unable to initialize postcar frame.\n");
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 42b08338d4ff..4cadc68a8939 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -152,6 +152,9 @@ asmlinkage void car_stage_entry(void)
 	if (romstage_handoff_init(s3_resume))
 		printk(BIOS_ERR, "Failed to set romstage handoff data\n");
 
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
 	post_code(0x44);
 	if (postcar_frame_init(&pcf, 0))
 		die("Unable to initialize postcar frame.\n");
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 8361bb197282..6bf8aac9aff8 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #if CONFIG(EC_GOOGLE_CHROMEEC)
 #include <ec/google/chromeec/ec.h>
 #endif
@@ -146,6 +147,9 @@ static void romstage_main(uint64_t tsc, uint32_t bist)
 	/* Call into mainboard. */
 	mainboard_romstage_entry(&rp);
 
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
 	prepare_and_run_postcar(&early_mtrrs);
 	/* We do not return here. */
 }
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 523d1f56f40d..44c2392abc19 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -15,10 +15,6 @@ source "src/soc/intel/common/pch/Kconfig"
 comment "Intel SoC Common coreboot stages"
 source "src/soc/intel/common/basecode/Kconfig"
 
-config DISPLAY_SMM_MEMORY_MAP
-	bool "SMM: Display the SMM memory map"
-	default n
-
 config SOC_INTEL_COMMON_RESET
 	bool
 	default n
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index 52f4dc9d63e6..35b531a4652d 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -24,6 +24,7 @@
 #include <console/usb.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <timestamp.h>
@@ -255,9 +256,11 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
 
 	romstage_handoff_init(prev_sleep_state == ACPI_S3);
 
-	post_code(0x4f);
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
 
 	/* Load the ramstage. */
+	post_code(0x4f);
 	run_ramstage();
 	while (1);
 }
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 3b74a1cb693d..1f71c9828310 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <console/usb.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <program_loading.h>
 #include <timestamp.h>
 #include <version.h>
@@ -169,6 +170,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
 	if (!CONFIG(FSP_MEMORY_DOWN))
 		save_dimm_info();
 
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
+
 	/* Load the ramstage. */
 	post_code(0x4e);
 	run_ramstage();
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 2c2427eed1c9..f52a75205ae6 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -31,6 +31,7 @@
 #include "southbridge/intel/fsp_rangeley/gpio.h"
 #include "southbridge/intel/fsp_rangeley/romstage.h"
 #include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
 #include "gpio.h"
 
 void main(FSP_INFO_HEADER *fsp_info_header)
@@ -121,9 +122,11 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
 	*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
 	post_code(0x4e);
 
-	post_code(0x4f);
+	if (CONFIG(SMM_TSEG))
+		smm_list_regions();
 
 	/* Load the ramstage. */
+	post_code(0x4f);
 	run_ramstage();
 	while (1);
 }