diff options
| author | Vinod Polimera <vpolimer@codeaurora.org> | 2021-09-29 10:23:28 +0530 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2022-01-12 17:35:21 +0000 |
| commit | 878d3723fbbaced4d53ebbdfdf89ef7bef06a06a (patch) | |
| tree | ed5a1a69e954f39904ad1aeca911c1cb46c3f2fc | |
| parent | ec58c013724ec639e491766628f1261de66f1363 (diff) | |
| download | coreboot-878d3723fbbaced4d53ebbdfdf89ef7bef06a06a.tar.gz coreboot-878d3723fbbaced4d53ebbdfdf89ef7bef06a06a.tar.bz2 coreboot-878d3723fbbaced4d53ebbdfdf89ef7bef06a06a.zip | |
sc7180: Update video mode active horizontal/vertical/total calculations
Remove vbp & hbp as the names are misleading and use edid variables
to simplify the video mode active and total calculations.
Change-Id: I9ccafabe226fa53c6f82e32413d4c00a0b4531be
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
| -rw-r--r-- | src/soc/qualcomm/sc7180/display/dsi.c | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/src/soc/qualcomm/sc7180/display/dsi.c b/src/soc/qualcomm/sc7180/display/dsi.c index 15d36ed0b8bb..48dc2b395d68 100644 --- a/src/soc/qualcomm/sc7180/display/dsi.c +++ b/src/soc/qualcomm/sc7180/display/dsi.c @@ -100,7 +100,6 @@ void mdss_dsi_video_mode_config(struct edid *edid, uint32_t bpp) { uint16_t dst_format; uint8_t lane_en = 15; /* Enable 4 lanes by default */ - uint16_t hfp, hbp, vfp, vbp; switch (bpp) { case 16: @@ -115,23 +114,17 @@ void mdss_dsi_video_mode_config(struct edid *edid, uint32_t bpp) break; } - hfp = edid->mode.hso; - hbp = edid->mode.hbl - edid->mode.hso; - vfp = edid->mode.vso; - vbp = edid->mode.vbl - edid->mode.vso; - write32(&dsi0->video_mode_active_h, - ((edid->mode.ha + hbp) << 16) | - hbp); + ((edid->mode.ha + edid->mode.hbl - edid->mode.hso) << 16) | + (edid->mode.hbl - edid->mode.hso)); write32(&dsi0->video_mode_active_v, - ((edid->mode.va + vbp) << 16) | (vbp)); + ((edid->mode.va + edid->mode.vbl - edid->mode.vso) << 16) | + (edid->mode.vbl - edid->mode.vso)); write32(&dsi0->video_mode_active_total, - ((edid->mode.va + vfp + - vbp - 1) << 16) | - (edid->mode.ha + hfp + - hbp - 1)); + ((edid->mode.va + edid->mode.vbl - 1) << 16) | + (edid->mode.ha + edid->mode.hbl - 1)); write32(&dsi0->video_mode_active_hsync, (edid->mode.hspw << 16)); write32(&dsi0->video_mode_active_vsync, 0x0); |