AGESA: Remove heap allocations from OemCustomize.c

We can simply declare these structures const.

Change-Id: I637c60cc2f83e682bd5e415b674f6e27c705ac91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

24 files changed, 624 insertions, 1845 deletions

diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c
index 499c7731366f..2b32fb18cb88 100644
--- a/src/mainboard/amd/inagua/OemCustomize.c
+++ b/src/mainboard/amd/inagua/OemCustomize.c
@@ -15,116 +15,63 @@
 
 #include "PlatformGnbPcieComplex.h"
 
-#include <string.h>
+#include <AGESA.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
 
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *	OemCustomizeInitEarly
- *
- *	Description:
- *	This stub function will call the host environment through the binary block
- *	interface (call-out port) to provide a user hook opportunity
- *
- *	Parameters:
- *	@param[in]		*InitEarly
- *
- *	@retval		 VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	AGESA_STATUS		 Status;
-	VOID				 *BrazosPcieComplexListPtr;
-	VOID				 *BrazosPciePortPtr;
-	VOID				 *BrazosPcieDdiPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-	PCIe_PORT_DESCRIPTOR PortList[] = {
-		// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-		}
-	};
-
-	PCIe_DDI_DESCRIPTOR DdiList[] = {
-		// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-			PCIE_DDI_DATA_INITIALIZER(ConnectorTypeLvds, Aux1, Hdp1)
-		},
-		// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-			PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux2, Hdp2)
-		}
-	};
-
-	PCIe_COMPLEX_DESCRIPTOR Brazos = {
-		DESCRIPTOR_TERMINATE_LIST,
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
+	{
 		0,
-		&PortList[0],
-		&DdiList[0]
-	};
-
-	// GNB PCIe topology Porting
-
-	//
-	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	//
-	AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(Brazos);
-	BrazosPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(PortList);
-	BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
-	memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
-	memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+	}
+};
 
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeLvds, Aux1, Hdp1)
+	},
+	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux2, Hdp2)
+	}
+};
 
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
+};
 
-	InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
-	InitEarly->GnbConfig.PsppPolicy      = 0;
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+	InitEarly->GnbConfig.PsppPolicy		= 0;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c
index 0edbf5eb3f00..9ed7cee723d1 100644
--- a/src/mainboard/amd/olivehill/OemCustomize.c
+++ b/src/mainboard/amd/olivehill/OemCustomize.c
@@ -14,13 +14,10 @@
  */
 
 #include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
 
 #include <northbridge/amd/agesa/state_machine.h>
 
-
 static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
@@ -101,7 +98,6 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 	.DdiLinkList  = DdiList
 };
 
-
 void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 {
 	FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
@@ -109,44 +105,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 	FchReset->Xhci1Enable = FALSE;
 }
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This is the stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
-	AGESA_STATUS            Status;
-	PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-	/* GNB PCIe topology Porting */
-
-	/*  */
-	/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
-	/*  */
-	AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	PcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-	LibAmdMemCopy  (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
-	InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c
index b358241af92f..21847f91a701 100644
--- a/src/mainboard/amd/parmer/OemCustomize.c
+++ b/src/mainboard/amd/parmer/OemCustomize.c
@@ -14,8 +14,6 @@
  */
 
 #include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
 
 #include <northbridge/amd/agesa/state_machine.h>
@@ -145,54 +143,16 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 	FchReset->Xhci1Enable = FALSE;
 }
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
+};
 
 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
-	AGESA_STATUS            Status;
-	PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-	/* GNB PCIe topology Porting */
-
-	/*  */
-	/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
-	/*  */
-	AllocHeapParams.RequestedBufferSize = sizeof(PCIe_COMPLEX_DESCRIPTOR);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	PcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	LibAmdMemFill (PcieComplexListPtr,
-		       0,
-		       sizeof(PCIe_COMPLEX_DESCRIPTOR),
-		       &InitEarly->StdHeader);
-
-	PcieComplexListPtr->Flags        = DESCRIPTOR_TERMINATE_LIST;
-	PcieComplexListPtr->SocketId     = 0;
-	PcieComplexListPtr->PciePortList = PortList;
-	PcieComplexListPtr->DdiLinkList  = DdiList;
-
-	InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c
index 6087eb0597ef..7625940215dc 100644
--- a/src/mainboard/amd/persimmon/OemCustomize.c
+++ b/src/mainboard/amd/persimmon/OemCustomize.c
@@ -15,121 +15,71 @@
 
 #include "PlatformGnbPcieComplex.h"
 
-#include <string.h>
+#include <AGESA.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
 
 
-/**
- *	OemCustomizeInitEarly
- *
- *	Description:
- *	This stub function will call the host environment through the binary block
- *	interface (call-out port) to provide a user hook opportunity
- *
- *	Parameters:
- *	@param[in]		*InitEarly
- *
- *	@retval		 VOID
- *
- **/
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	AGESA_STATUS		 Status;
-	VOID				 *BrazosPcieComplexListPtr;
-	VOID				 *BrazosPciePortPtr;
-	VOID				 *BrazosPcieDdiPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-PCIe_PORT_DESCRIPTOR PortList[] = {
-		// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-		}
-};
-
-PCIe_DDI_DESCRIPTOR DdiList[] = {
-		// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-			//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
-			{ConnectorTypeLvds, Aux1, Hdp1}
-		},
-		// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-			//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-			{ConnectorTypeDP, Aux2, Hdp2}
-		}
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+	}
 };
 
-PCIe_COMPLEX_DESCRIPTOR Brazos = {
-		DESCRIPTOR_TERMINATE_LIST,
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+	{
 		0,
-		&PortList[0],
-		&DdiList[0]
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
+		{ConnectorTypeLvds, Aux1, Hdp1}
+	},
+	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
+		{ConnectorTypeDP, Aux2, Hdp2}
+	}
 };
 
-	// GNB PCIe topology Porting
-
-	//
-	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	//
-	AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	BrazosPcieComplexListPtr	=	(PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(Brazos);
-	BrazosPciePortPtr		 =	(PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(PortList);
-	BrazosPcieDdiPtr			=	(PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
-	memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
-	memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
-
-
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =	(PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList	=	(PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
+};
 
-	InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 	InitEarly->GnbConfig.PsppPolicy		= 0;
 }
 
diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c
index 649765e607ed..b4bcbac5bf32 100644
--- a/src/mainboard/amd/south_station/OemCustomize.c
+++ b/src/mainboard/amd/south_station/OemCustomize.c
@@ -15,124 +15,69 @@
 
 #include "PlatformGnbPcieComplex.h"
 
-#include <string.h>
+#include <AGESA.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
 
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-  AGESA_STATUS         Status;
-  VOID                 *BrazosPcieComplexListPtr;
-  VOID                 *BrazosPciePortPtr;
-  VOID                 *BrazosPcieDdiPtr;
-
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-PCIe_PORT_DESCRIPTOR PortList[] = {
-        // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-        {
-          0,
-          PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-          PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
-        },
-	#if 1
-        // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-        {
-          0,
-          PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-          PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-        {
-          0,
-          PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-          PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-        {
-          0,
-          PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-          PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
-        },
-	#endif
-        // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-        {
-          DESCRIPTOR_TERMINATE_LIST,
-          PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-          PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-        }
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+	}
 };
 
-PCIe_DDI_DESCRIPTOR DdiList[] = {
-        /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */
-        {
-          0,
-          PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-          PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
-        },
-        /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 VGA */
-        {
-          DESCRIPTOR_TERMINATE_LIST,
-          PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-          PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux1, Hdp1)
-        }
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	/* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
+	},
+	/* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 VGA */
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux1, Hdp1)
+	}
 };
 
-PCIe_COMPLEX_DESCRIPTOR Brazos = {
-        DESCRIPTOR_TERMINATE_LIST,
-        0,
-        &PortList[0],
-        &DdiList[0]
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
 };
 
-  // GNB PCIe topology Porting
-
-  //
-  // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-  //
-  AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
-
-  AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-  BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-  AllocHeapParams.BufferPtr += sizeof(Brazos);
-  BrazosPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-  AllocHeapParams.BufferPtr += sizeof(PortList);
-  BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
-	memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
-	memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
-
-
-  ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-  ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
-
-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
-  InitEarly->GnbConfig.PsppPolicy      = 0;
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+	InitEarly->GnbConfig.PsppPolicy		= 0;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c
index 5229b05aec13..c035722c58e3 100644
--- a/src/mainboard/amd/thatcher/OemCustomize.c
+++ b/src/mainboard/amd/thatcher/OemCustomize.c
@@ -14,8 +14,6 @@
  */
 
 #include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
 
 #include <northbridge/amd/agesa/state_machine.h>
@@ -137,13 +135,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
 	},
 };
 
-static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
-        DESCRIPTOR_TERMINATE_LIST,
-        0,
-        &PortList[0],
-        &DdiList[0]
-};
-
 void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 {
 	FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
@@ -151,74 +142,16 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 	FchReset->Xhci1Enable = FALSE;
 }
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
+};
 
 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
-	AGESA_STATUS         Status;
-	VOID                 *TrinityPcieComplexListPtr;
-	VOID                 *TrinityPciePortPtr;
-	VOID                 *TrinityPcieDdiPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-	// GNB PCIe topology Porting
-
-	//
-	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	//
-	AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	TrinityPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(Trinity);
-	TrinityPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(PortList);
-	TrinityPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	LibAmdMemFill (TrinityPcieComplexListPtr,
-		       0,
-		       sizeof(Trinity),
-		       &InitEarly->StdHeader);
-
-	LibAmdMemFill (TrinityPciePortPtr,
-		       0,
-		       sizeof(PortList),
-		       &InitEarly->StdHeader);
-
-	LibAmdMemFill (TrinityPcieDdiPtr,
-		       0,
-		       sizeof(DdiList),
-		       &InitEarly->StdHeader);
-
-	LibAmdMemCopy  (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader);
-	LibAmdMemCopy  (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
-	LibAmdMemCopy  (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
-
-	((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;
-	((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
-
-	InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c
index 04d509f0e567..bb377fa3c698 100644
--- a/src/mainboard/amd/torpedo/OemCustomize.c
+++ b/src/mainboard/amd/torpedo/OemCustomize.c
@@ -14,12 +14,8 @@
  */
 
 
-#include <string.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include <vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
-#include "amdlib.h"
-
 
 static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	// Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
@@ -75,83 +71,17 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
 	}
 };
 
-static const PCIe_COMPLEX_DESCRIPTOR Llano = {
-	DESCRIPTOR_TERMINATE_LIST,
-	0,
-	&PortList[0],
-	&DdiList[0]
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
 };
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
-	AGESA_STATUS         Status;
-	VOID                 *LlanoPcieComplexListPtr;
-	VOID                 *LlanoPciePortPtr;
-	VOID                 *LlanoPcieDdiPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-	// GNB PCIe topology Porting
-
-	//
-	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	//
-	AllocHeapParams.RequestedBufferSize = sizeof(Llano) + sizeof(PortList) + sizeof(DdiList);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	LlanoPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(Llano);
-	LlanoPciePortPtr        = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(PortList);
-	LlanoPcieDdiPtr         = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	LibAmdMemFill (LlanoPcieComplexListPtr,
-	                 0,
-	                 sizeof(Llano),
-	                 &InitEarly->StdHeader);
-
-	LibAmdMemFill (LlanoPciePortPtr,
-	                 0,
-	                 sizeof(PortList),
-	                 &InitEarly->StdHeader);
-
-	LibAmdMemFill (LlanoPcieDdiPtr,
-	                 0,
-	                 sizeof(DdiList),
-	                 &InitEarly->StdHeader);
-
-	LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof(Llano), &InitEarly->StdHeader);
-	LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
-	LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
-
-
-	((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr;
-	((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)LlanoPcieDdiPtr;
-
-	InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr;
-	InitEarly->GnbConfig.PsppPolicy      = 0;
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+	InitEarly->GnbConfig.PsppPolicy		= 0;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c
index 82afd838cd1c..43b2491922f4 100644
--- a/src/mainboard/amd/union_station/OemCustomize.c
+++ b/src/mainboard/amd/union_station/OemCustomize.c
@@ -14,48 +14,19 @@
  */
 
 #include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
 #include "PlatformGnbPcieComplex.h"
 
 #include <string.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-  AGESA_STATUS         Status;
-  VOID                 *BrazosPcieComplexListPtr;
-  VOID                 *BrazosPciePortPtr;
-  VOID                 *BrazosPcieDdiPtr;
-
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-PCIe_PORT_DESCRIPTOR PortList[] = {
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
         // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
         {
           0,
           PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
           PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
         },
-	#if 1
         // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
         {
           0,
@@ -74,7 +45,6 @@ PCIe_PORT_DESCRIPTOR PortList[] = {
           PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
           PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
         },
-	#endif
         // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
         {
           DESCRIPTOR_TERMINATE_LIST,
@@ -83,60 +53,34 @@ PCIe_PORT_DESCRIPTOR PortList[] = {
         }
 };
 
-PCIe_DDI_DESCRIPTOR DdiList[] = {
-        // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-        {
-          0,
-          PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-          //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
-          {ConnectorTypeHDMI, Aux1, Hdp1}
-        },
-        // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-        {
-          DESCRIPTOR_TERMINATE_LIST,
-          PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-          //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-          {ConnectorTypeHDMI, Aux2, Hdp2}
-        }
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
+		{ConnectorTypeHDMI, Aux1, Hdp1}
+	},
+	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
+		{ConnectorTypeHDMI, Aux2, Hdp2}
+	}
 };
 
-PCIe_COMPLEX_DESCRIPTOR Brazos = {
-        DESCRIPTOR_TERMINATE_LIST,
-        0,
-        &PortList[0],
-        &DdiList[0]
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
 };
 
-  // GNB PCIe topology Porting
-
-  //
-  // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-  //
-  AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
-
-  AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-  BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-  AllocHeapParams.BufferPtr += sizeof(Brazos);
-  BrazosPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-  AllocHeapParams.BufferPtr += sizeof(PortList);
-  BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
-	memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
-	memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
-
-
-  ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-  ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
-
-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
-  InitEarly->GnbConfig.PsppPolicy      = 0;
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+	InitEarly->GnbConfig.PsppPolicy		= 0;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/asrock/e350m1/OemCustomize.c b/src/mainboard/asrock/e350m1/OemCustomize.c
index 50c37e4556b8..2ce42e029a11 100644
--- a/src/mainboard/asrock/e350m1/OemCustomize.c
+++ b/src/mainboard/asrock/e350m1/OemCustomize.c
@@ -14,109 +14,54 @@
  */
 
 #include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
 #include "PlatformGnbPcieComplex.h"
 
-#include <string.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-  AGESA_STATUS         Status;
-  VOID                 *BrazosPcieComplexListPtr;
-  VOID                 *BrazosPciePortPtr;
-  VOID                 *BrazosPcieDdiPtr;
-
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-PCIe_PORT_DESCRIPTOR PortList[] = {
-        // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-        {
-          0,
-          PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
-          PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-        {
-          DESCRIPTOR_TERMINATE_LIST,
-          PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-          PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-        }
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+	}
 };
 
-PCIe_DDI_DESCRIPTOR DdiList[] = {
-        // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-        {
-          0,
-          PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-          //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
-          {ConnectorTypeDP, Aux1, Hdp1}
-        },
-        // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-        {
-          DESCRIPTOR_TERMINATE_LIST,
-          PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-          //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-          {ConnectorTypeDP, Aux2, Hdp2}
-        }
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
+		{ConnectorTypeDP, Aux1, Hdp1}
+	},
+	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
+		{ConnectorTypeDP, Aux2, Hdp2}
+	}
 };
 
-PCIe_COMPLEX_DESCRIPTOR Brazos = {
-        DESCRIPTOR_TERMINATE_LIST,
-        0,
-        &PortList[0],
-        &DdiList[0]
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
 };
 
-  // GNB PCIe topology Porting
-
-  //
-  // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-  //
-  AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
-
-  AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-  BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-  AllocHeapParams.BufferPtr += sizeof(Brazos);
-  BrazosPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-  AllocHeapParams.BufferPtr += sizeof(PortList);
-  BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
-	memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
-	memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
-
-
-  ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-  ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
-
-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
-  InitEarly->GnbConfig.PsppPolicy      = 0;
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+	InitEarly->GnbConfig.PsppPolicy		= 0;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/asrock/imb-a180/OemCustomize.c b/src/mainboard/asrock/imb-a180/OemCustomize.c
index 19acffb93e7e..0e3c337deab4 100644
--- a/src/mainboard/asrock/imb-a180/OemCustomize.c
+++ b/src/mainboard/asrock/imb-a180/OemCustomize.c
@@ -14,8 +14,6 @@
  */
 
 #include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
 
 #include <northbridge/amd/agesa/state_machine.h>
@@ -108,44 +106,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 	FchReset->Xhci1Enable = FALSE;
 }
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This is the stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
-	AGESA_STATUS            Status;
-	PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-	/* GNB PCIe topology Porting */
-
-	/*  */
-	/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
-	/*  */
-	AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	PcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-	LibAmdMemCopy  (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
-	InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c
index 5ecba8ee6afa..954268f73f8d 100644
--- a/src/mainboard/asus/f2a85-m/OemCustomize.c
+++ b/src/mainboard/asus/f2a85-m/OemCustomize.c
@@ -15,13 +15,10 @@
 
 #include "Porting.h"
 #include "AGESA.h"
-#include "amdlib.h"
 
 #include <northbridge/amd/agesa/state_machine.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
 
-
 /*
  * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
  *
@@ -115,11 +112,11 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
 	},
 };
 
-static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
-        DESCRIPTOR_TERMINATE_LIST,
-        0,
-        &PortList[0],
-        &DdiList[0]
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
 };
 
 void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
@@ -129,73 +126,10 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 	FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
 }
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
-	AGESA_STATUS         Status;
-	VOID                 *TrinityPcieComplexListPtr;
-	VOID                 *TrinityPciePortPtr;
-	VOID                 *TrinityPcieDdiPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-	// GNB PCIe topology Porting
-
-	//
-	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	//
-	AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList);
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	TrinityPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(Trinity);
-	TrinityPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(PortList);
-	TrinityPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	LibAmdMemFill (TrinityPcieComplexListPtr,
-		       0,
-		       sizeof(Trinity),
-		       &InitEarly->StdHeader);
-
-	LibAmdMemFill (TrinityPciePortPtr,
-		       0,
-		       sizeof(PortList),
-		       &InitEarly->StdHeader);
-
-	LibAmdMemFill (TrinityPcieDdiPtr,
-		       0,
-		       sizeof(DdiList),
-		       &InitEarly->StdHeader);
-
-	LibAmdMemCopy  (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader);
-	LibAmdMemCopy  (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
-	LibAmdMemCopy  (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
-
-	((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;
-	((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
-
-	InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+	InitEarly->GnbConfig.PsppPolicy		= 0;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c
index 9b248cf59a50..f9cb232ef630 100644
--- a/src/mainboard/bap/ode_e20XX/OemCustomize.c
+++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c
@@ -14,8 +14,6 @@
  */
 
 #include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
 
 #include <northbridge/amd/agesa/state_machine.h>
@@ -93,44 +91,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 	FchReset->Xhci1Enable = FALSE;
 }
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This is the stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
-	AGESA_STATUS            Status;
-	PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-	/* GNB PCIe topology Porting */
-
-	/*  */
-	/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
-	/*  */
-	AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	PcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-	LibAmdMemCopy  (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
-	InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/biostar/am1ml/OemCustomize.c b/src/mainboard/biostar/am1ml/OemCustomize.c
index dc5219cd1720..80528c3ff592 100644
--- a/src/mainboard/biostar/am1ml/OemCustomize.c
+++ b/src/mainboard/biostar/am1ml/OemCustomize.c
@@ -14,13 +14,10 @@
  */
 
 #include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
 
 #include <northbridge/amd/agesa/state_machine.h>
 
-
 static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
@@ -113,44 +110,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 	FchReset->IdeEnable = 0;
 }
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This is the stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
-	AGESA_STATUS            Status;
-	PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-	/* GNB PCIe topology Porting */
-
-	/*  */
-	/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
-	/*  */
-	AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	PcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-	LibAmdMemCopy  (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
-	InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c
index 6087eb0597ef..93adb3416553 100644
--- a/src/mainboard/elmex/pcm205400/OemCustomize.c
+++ b/src/mainboard/elmex/pcm205400/OemCustomize.c
@@ -15,121 +15,70 @@
 
 #include "PlatformGnbPcieComplex.h"
 
-#include <string.h>
+#include <AGESA.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
 
-
-/**
- *	OemCustomizeInitEarly
- *
- *	Description:
- *	This stub function will call the host environment through the binary block
- *	interface (call-out port) to provide a user hook opportunity
- *
- *	Parameters:
- *	@param[in]		*InitEarly
- *
- *	@retval		 VOID
- *
- **/
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	AGESA_STATUS		 Status;
-	VOID				 *BrazosPcieComplexListPtr;
-	VOID				 *BrazosPciePortPtr;
-	VOID				 *BrazosPcieDdiPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-PCIe_PORT_DESCRIPTOR PortList[] = {
-		// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-		}
-};
-
-PCIe_DDI_DESCRIPTOR DdiList[] = {
-		// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-			//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
-			{ConnectorTypeLvds, Aux1, Hdp1}
-		},
-		// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-			//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-			{ConnectorTypeDP, Aux2, Hdp2}
-		}
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+	}
 };
 
-PCIe_COMPLEX_DESCRIPTOR Brazos = {
-		DESCRIPTOR_TERMINATE_LIST,
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+	{
 		0,
-		&PortList[0],
-		&DdiList[0]
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
+		{ConnectorTypeLvds, Aux1, Hdp1}
+	},
+	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
+		{ConnectorTypeDP, Aux2, Hdp2}
+	}
 };
 
-	// GNB PCIe topology Porting
-
-	//
-	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	//
-	AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	BrazosPcieComplexListPtr	=	(PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(Brazos);
-	BrazosPciePortPtr		 =	(PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(PortList);
-	BrazosPcieDdiPtr			=	(PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
-	memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
-	memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
-
-
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =	(PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList	=	(PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
+};
 
-	InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 	InitEarly->GnbConfig.PsppPolicy		= 0;
 }
 
diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c
index ec988dba191f..acce8238272a 100644
--- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c
+++ b/src/mainboard/gizmosphere/gizmo/OemCustomize.c
@@ -15,126 +15,71 @@
  */
 
 #include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
 #include "PlatformGnbPcieComplex.h"
-#include "Filecode.h"
 
-#include <string.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *	OemCustomizeInitEarly
- *
- *	Description:
- *	This stub function will call the host environment through the binary block
- *	interface (call-out port) to provide a user hook opportunity
- *
- *	Parameters:
- *	@param[in]		*InitEarly
- *
- *	@retval		 VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	AGESA_STATUS		 Status;
-	VOID				 *BrazosPcieComplexListPtr;
-	VOID				 *BrazosPciePortPtr;
-	VOID				 *BrazosPcieDdiPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-PCIe_PORT_DESCRIPTOR PortList[] = {
-		// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-		}
-};
-
-PCIe_DDI_DESCRIPTOR DdiList[] = {
-		// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-			//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
-			{ConnectorTypeDP, Aux1, Hdp1}
-		},
-		// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-			//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-			{ConnectorTypeDP, Aux2, Hdp2}
-		}
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+	}
 };
 
-PCIe_COMPLEX_DESCRIPTOR Brazos = {
-		DESCRIPTOR_TERMINATE_LIST,
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+	{
 		0,
-		&PortList[0],
-		&DdiList[0]
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
+		{ConnectorTypeDP, Aux1, Hdp1}
+	},
+	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
+		{ConnectorTypeDP, Aux2, Hdp2}
+	}
 };
 
-	// GNB PCIe topology Porting
-
-	//
-	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	//
-	AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	BrazosPcieComplexListPtr	=	(PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(Brazos);
-	BrazosPciePortPtr		 =	(PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(PortList);
-	BrazosPcieDdiPtr			=	(PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
-	memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
-	memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
-
-
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =	(PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList	=	(PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
+};
 
-	InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 	InitEarly->GnbConfig.PsppPolicy		= 0;
 }
 
diff --git a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c
index f51072b317cd..8b957a0f34b8 100644
--- a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c
+++ b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c
@@ -14,13 +14,10 @@
  */
 
 #include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
 
 #include <northbridge/amd/agesa/state_machine.h>
 
-
 static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
@@ -102,44 +99,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 	FchReset->Xhci1Enable = FALSE;
 }
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This is the stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
-	AGESA_STATUS            Status;
-	PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-	/* GNB PCIe topology Porting */
-
-	/*  */
-	/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
-	/*  */
-	AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	PcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-	LibAmdMemCopy  (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
-	InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/hp/abm/OemCustomize.c b/src/mainboard/hp/abm/OemCustomize.c
index ea325d3617fe..9f35016a5304 100644
--- a/src/mainboard/hp/abm/OemCustomize.c
+++ b/src/mainboard/hp/abm/OemCustomize.c
@@ -15,13 +15,10 @@
  */
 
 #include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
 
 #include <northbridge/amd/agesa/state_machine.h>
 
-
 static const PCIe_PORT_DESCRIPTOR PortList[] = {
 	{
 		0,
@@ -103,45 +100,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 	FchReset->Xhci1Enable = FALSE;
 }
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This is the stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      **PeiServices
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
-	AGESA_STATUS            Status;
-	PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-	/* GNB PCIe topology Porting */
-
-	/*  */
-	/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
-	/*  */
-	AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	PcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-	LibAmdMemCopy  (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
-	InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
index af7f3de8f923..d0fe4017a8f7 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
@@ -15,10 +15,8 @@
 
 #include "Porting.h"
 #include "AGESA.h"
-#include "amdlib.h"
 
 #include <northbridge/amd/agesa/state_machine.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
 
 
@@ -146,54 +144,16 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 	FchReset->Xhci1Enable = FALSE;
 }
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
+};
 
 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
-	AGESA_STATUS            Status;
-	PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-	/* GNB PCIe topology Porting */
-
-	/*  */
-	/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
-	/*  */
-	AllocHeapParams.RequestedBufferSize = sizeof(PCIe_COMPLEX_DESCRIPTOR);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	PcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	LibAmdMemFill (PcieComplexListPtr,
-		       0,
-		       sizeof(PCIe_COMPLEX_DESCRIPTOR),
-		       &InitEarly->StdHeader);
-
-	PcieComplexListPtr->Flags        = DESCRIPTOR_TERMINATE_LIST;
-	PcieComplexListPtr->SocketId     = 0;
-	PcieComplexListPtr->PciePortList = PortList;
-	PcieComplexListPtr->DdiLinkList  = DdiList;
-
-	InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
index c0fd9604eacb..d2d9202f8f02 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
@@ -16,165 +16,106 @@
 
 #include "PlatformGnbPcieComplex.h"
 
-#include <string.h>
+#include <AGESA.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
 
-
-/**
- *	OemCustomizeInitEarly
- *
- *	Description:
- *	This stub function will call the host environment through the binary block
- *	interface (call-out port) to provide a user hook opportunity
- *
- *	Parameters:
- *	@param[in]		*InitEarly
- *
- **/
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	AGESA_STATUS	 Status;
-	void	*BrazosPcieComplexListPtr;
-	void	*BrazosPciePortPtr;
-	void	*BrazosPcieDdiPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-/**
- * @brief Initialize Port descriptors
- */
-PCIe_PORT_DESCRIPTOR PortList[] = {
-		/* (PCIe port, Lanes 4, PCI Device Number 4, ...) */
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT,
-							GNB_GPP_PORT4_CHANNEL_TYPE,
-							4,
-							GNB_GPP_PORT4_HOTPLUG_SUPPORT,
-							GNB_GPP_PORT4_SPEED_MODE,
-							GNB_GPP_PORT4_SPEED_MODE,
-							GNB_GPP_PORT4_LINK_ASPM,
-							46)
-		},
-		/* (PCIe port, Lanes 5, PCI Device Number 5, ...) */
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT,
-							GNB_GPP_PORT5_CHANNEL_TYPE,
-							5,
-							GNB_GPP_PORT5_HOTPLUG_SUPPORT,
-							GNB_GPP_PORT5_SPEED_MODE,
-							GNB_GPP_PORT5_SPEED_MODE,
-							GNB_GPP_PORT5_LINK_ASPM,
-							46)
-		},
-		/* (PCIe port, Lanes 6, PCI Device Number 6, ...) */
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT,
-							GNB_GPP_PORT6_CHANNEL_TYPE,
-							6,
-							GNB_GPP_PORT6_HOTPLUG_SUPPORT,
-							GNB_GPP_PORT6_SPEED_MODE,
-							GNB_GPP_PORT6_SPEED_MODE,
-							GNB_GPP_PORT6_LINK_ASPM,
-							46)
-		},
-		/* (PCIe port, Lanes 7, PCI Device Number 7, ...) */
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT,
-							GNB_GPP_PORT7_CHANNEL_TYPE,
-							7,
-							GNB_GPP_PORT7_HOTPLUG_SUPPORT,
-							GNB_GPP_PORT7_SPEED_MODE,
-							GNB_GPP_PORT7_SPEED_MODE,
-							GNB_GPP_PORT7_LINK_ASPM,
-							0)
-		},
-		/* (PCIe port, Lanes 8, PCI Device Number 8, ...) */
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT,
-							GNB_GPP_PORT8_CHANNEL_TYPE,
-							8,
-							GNB_GPP_PORT8_HOTPLUG_SUPPORT,
-							GNB_GPP_PORT8_SPEED_MODE,
-							GNB_GPP_PORT8_SPEED_MODE,
-							GNB_GPP_PORT8_LINK_ASPM,
-							0)
-		}
-};
-
-/**
- * @brief Initialize Ddi descriptors
- */
-PCIe_DDI_DESCRIPTOR DdiList[] = {
-		/* (DDI interface Lanes 8:11, DdA, ...) */
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-			/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) */
-			{ConnectorTypeLvds, Aux1, Hdp1}
-		},
-		/* (DDI interface Lanes 12:15, DdB, ...) */
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-			/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) */
-			{ConnectorTypeDP, Aux2, Hdp2}
-		}
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	/* (PCIe port, Lanes 4, PCI Device Number 4, ...) */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT,
+						GNB_GPP_PORT4_CHANNEL_TYPE,
+						4,
+						GNB_GPP_PORT4_HOTPLUG_SUPPORT,
+						GNB_GPP_PORT4_SPEED_MODE,
+						GNB_GPP_PORT4_SPEED_MODE,
+						GNB_GPP_PORT4_LINK_ASPM,
+						46)
+	},
+	/* (PCIe port, Lanes 5, PCI Device Number 5, ...) */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT,
+						GNB_GPP_PORT5_CHANNEL_TYPE,
+						5,
+						GNB_GPP_PORT5_HOTPLUG_SUPPORT,
+						GNB_GPP_PORT5_SPEED_MODE,
+						GNB_GPP_PORT5_SPEED_MODE,
+						GNB_GPP_PORT5_LINK_ASPM,
+						46)
+	},
+	/* (PCIe port, Lanes 6, PCI Device Number 6, ...) */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT,
+						GNB_GPP_PORT6_CHANNEL_TYPE,
+						6,
+						GNB_GPP_PORT6_HOTPLUG_SUPPORT,
+						GNB_GPP_PORT6_SPEED_MODE,
+						GNB_GPP_PORT6_SPEED_MODE,
+						GNB_GPP_PORT6_LINK_ASPM,
+						46)
+	},
+	/* (PCIe port, Lanes 7, PCI Device Number 7, ...) */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT,
+						GNB_GPP_PORT7_CHANNEL_TYPE,
+						7,
+						GNB_GPP_PORT7_HOTPLUG_SUPPORT,
+						GNB_GPP_PORT7_SPEED_MODE,
+						GNB_GPP_PORT7_SPEED_MODE,
+						GNB_GPP_PORT7_LINK_ASPM,
+						0)
+	},
+	/* (PCIe port, Lanes 8, PCI Device Number 8, ...) */
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT,
+						GNB_GPP_PORT8_CHANNEL_TYPE,
+						8,
+						GNB_GPP_PORT8_HOTPLUG_SUPPORT,
+						GNB_GPP_PORT8_SPEED_MODE,
+						GNB_GPP_PORT8_SPEED_MODE,
+						GNB_GPP_PORT8_LINK_ASPM,
+						0)
+	}
 };
 
-PCIe_COMPLEX_DESCRIPTOR Brazos = {
-		DESCRIPTOR_TERMINATE_LIST,
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	/* (DDI interface Lanes 8:11, DdA, ...) */
+	{
 		0,
-		&PortList[0],
-		&DdiList[0]
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) */
+		{ConnectorTypeLvds, Aux1, Hdp1}
+	},
+	/* (DDI interface Lanes 12:15, DdB, ...) */
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) */
+		{ConnectorTypeDP, Aux2, Hdp2}
+	}
 };
 
-	/**
-	 * @brief GNB PCIe topology Porting
-	 *
-	 * Allocate buffer for
-	 * PCIe_COMPLEX_DESCRIPTOR, PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	 */
-	AllocHeapParams.RequestedBufferSize =
-		sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	BrazosPcieComplexListPtr =
-		(PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(Brazos);
-	BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(PortList);
-	BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
-	memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
-	memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
-
-	((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList =
-		(PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr;
-	((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->DdiLinkList =
-		(PCIe_DDI_DESCRIPTOR *) BrazosPcieDdiPtr;
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
+};
 
-	InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
-	InitEarly->GnbConfig.PsppPolicy = 0;
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+	InitEarly->GnbConfig.PsppPolicy		= 0;
 }
 
 /**
diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c
index af7f3de8f923..aaed339e96a2 100644
--- a/src/mainboard/lenovo/g505s/OemCustomize.c
+++ b/src/mainboard/lenovo/g505s/OemCustomize.c
@@ -15,10 +15,8 @@
 
 #include "Porting.h"
 #include "AGESA.h"
-#include "amdlib.h"
 
 #include <northbridge/amd/agesa/state_machine.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
 
 
@@ -139,6 +137,13 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
 	},
 };
 
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
+};
+
 void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 {
 	FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
@@ -146,54 +151,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 	FchReset->Xhci1Enable = FALSE;
 }
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
-	AGESA_STATUS            Status;
-	PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-	/* GNB PCIe topology Porting */
-
-	/*  */
-	/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
-	/*  */
-	AllocHeapParams.RequestedBufferSize = sizeof(PCIe_COMPLEX_DESCRIPTOR);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	PcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	LibAmdMemFill (PcieComplexListPtr,
-		       0,
-		       sizeof(PCIe_COMPLEX_DESCRIPTOR),
-		       &InitEarly->StdHeader);
-
-	PcieComplexListPtr->Flags        = DESCRIPTOR_TERMINATE_LIST;
-	PcieComplexListPtr->SocketId     = 0;
-	PcieComplexListPtr->PciePortList = PortList;
-	PcieComplexListPtr->DdiLinkList  = DdiList;
-
-	InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/lippert/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/OemCustomize.c
index 95f43b0b7468..2db584cd9d52 100644
--- a/src/mainboard/lippert/frontrunner-af/OemCustomize.c
+++ b/src/mainboard/lippert/frontrunner-af/OemCustomize.c
@@ -14,126 +14,71 @@
  */
 
 #include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
 #include "PlatformGnbPcieComplex.h"
 
-#include <string.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *	OemCustomizeInitEarly
- *
- *	Description:
- *	This stub function will call the host environment through the binary block
- *	interface (call-out port) to provide a user hook opportunity
- *
- *	Parameters:
- *	@param[in]		*InitEarly
- *
- *	@retval		 VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	AGESA_STATUS		 Status;
-	VOID				 *BrazosPcieComplexListPtr;
-	VOID				 *BrazosPciePortPtr;
-	VOID				 *BrazosPcieDdiPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-PCIe_PORT_DESCRIPTOR PortList[] = {
-		// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-		}
-};
-
-PCIe_DDI_DESCRIPTOR DdiList[] = {
-		// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-			//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
-			{ConnectorTypeTravisDpToLvds, Aux1, Hdp1}
-		},
-		// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-			//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-			{ConnectorTypeDP, Aux2, Hdp2}
-		}
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+	}
 };
 
-PCIe_COMPLEX_DESCRIPTOR Brazos = {
-		DESCRIPTOR_TERMINATE_LIST,
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+	{
 		0,
-		&PortList[0],
-		&DdiList[0]
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
+		{ConnectorTypeTravisDpToLvds, Aux1, Hdp1}
+	},
+	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
+		{ConnectorTypeDP, Aux2, Hdp2}
+	}
 };
 
-	// GNB PCIe topology Porting
-
-	//
-	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	//
-	AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	BrazosPcieComplexListPtr	=	(PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(Brazos);
-	BrazosPciePortPtr		 =	(PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(PortList);
-	BrazosPcieDdiPtr			=	(PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
-	memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
-	memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
-
-
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =	(PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList	=	(PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
+};
 
-	InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 	InitEarly->GnbConfig.PsppPolicy		= 0;
 }
 
diff --git a/src/mainboard/lippert/toucan-af/OemCustomize.c b/src/mainboard/lippert/toucan-af/OemCustomize.c
index 24bd91f0b86e..fe345d74c7e0 100644
--- a/src/mainboard/lippert/toucan-af/OemCustomize.c
+++ b/src/mainboard/lippert/toucan-af/OemCustomize.c
@@ -14,126 +14,71 @@
  */
 
 #include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
 #include <PlatformMemoryConfiguration.h>
 #include "PlatformGnbPcieComplex.h"
 
-#include <string.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *	OemCustomizeInitEarly
- *
- *	Description:
- *	This stub function will call the host environment through the binary block
- *	interface (call-out port) to provide a user hook opportunity
- *
- *	Parameters:
- *	@param[in]		*InitEarly
- *
- *	@retval		 VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	AGESA_STATUS		 Status;
-	VOID				 *BrazosPcieComplexListPtr;
-	VOID				 *BrazosPciePortPtr;
-	VOID				 *BrazosPcieDdiPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-PCIe_PORT_DESCRIPTOR PortList[] = {
-		// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-		}
-};
-
-PCIe_DDI_DESCRIPTOR DdiList[] = {
-		// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-			//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
-			{ConnectorTypeAutoDetect, Aux1, Hdp1}
-		},
-		// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-			//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-			{ConnectorTypeAutoDetect, Aux2, Hdp2}
-		}
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+	}
 };
 
-PCIe_COMPLEX_DESCRIPTOR Brazos = {
-		DESCRIPTOR_TERMINATE_LIST,
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+	{
 		0,
-		&PortList[0],
-		&DdiList[0]
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
+		{ConnectorTypeAutoDetect, Aux1, Hdp1}
+	},
+	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
+		{ConnectorTypeAutoDetect, Aux2, Hdp2}
+	}
 };
 
-	// GNB PCIe topology Porting
-
-	//
-	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	//
-	AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	BrazosPcieComplexListPtr	=	(PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(Brazos);
-	BrazosPciePortPtr		 =	(PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(PortList);
-	BrazosPcieDdiPtr			=	(PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
-	memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
-	memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
-
-
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =	(PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList	=	(PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
+};
 
-	InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 	InitEarly->GnbConfig.PsppPolicy		= 0;
 }
 
diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c
index 3c8d5c51b2dd..80e6c96751ed 100644
--- a/src/mainboard/msi/ms7721/OemCustomize.c
+++ b/src/mainboard/msi/ms7721/OemCustomize.c
@@ -16,10 +16,8 @@
 
 #include "Porting.h"
 #include "AGESA.h"
-#include "amdlib.h"
 
 #include <northbridge/amd/agesa/state_machine.h>
-#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
 
 
@@ -122,11 +120,11 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
 	},
 };
 
-static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
-        DESCRIPTOR_TERMINATE_LIST,
-        0,
-        &PortList[0],
-        &DdiList[0]
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
 };
 
 void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
@@ -136,73 +134,9 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 	FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
 }
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-
 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
-	AGESA_STATUS         Status;
-	VOID                 *TrinityPcieComplexListPtr;
-	VOID                 *TrinityPciePortPtr;
-	VOID                 *TrinityPcieDdiPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-	// GNB PCIe topology Porting
-
-	//
-	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	//
-	AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList);
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	TrinityPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(Trinity);
-	TrinityPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(PortList);
-	TrinityPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	LibAmdMemFill (TrinityPcieComplexListPtr,
-		       0,
-		       sizeof(Trinity),
-		       &InitEarly->StdHeader);
-
-	LibAmdMemFill (TrinityPciePortPtr,
-		       0,
-		       sizeof(PortList),
-		       &InitEarly->StdHeader);
-
-	LibAmdMemFill (TrinityPcieDdiPtr,
-		       0,
-		       sizeof(DdiList),
-		       &InitEarly->StdHeader);
-
-	LibAmdMemCopy  (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader);
-	LibAmdMemCopy  (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
-	LibAmdMemCopy  (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
-
-	((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;
-	((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
-
-	InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 }
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c
index 6220c30fe9b1..21fcdd244161 100644
--- a/src/mainboard/pcengines/apu1/OemCustomize.c
+++ b/src/mainboard/pcengines/apu1/OemCustomize.c
@@ -16,113 +16,53 @@
 
 #include "PlatformGnbPcieComplex.h"
 
-#include <string.h>
+#include <AGESA.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
 #include <PlatformMemoryConfiguration.h>
 
-/**
- *	OemCustomizeInitEarly
- *
- *	Description:
- *	This stub function will call the host environment through the binary block
- *	interface (call-out port) to provide a user hook opportunity
- *
- *	Parameters:
- *	@param[in]		*InitEarly
- *
- *	@retval		 VOID
- *
- **/
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	AGESA_STATUS		 Status;
-	VOID				 *BrazosPcieComplexListPtr;
-	VOID				 *BrazosPciePortPtr;
-	VOID				 *BrazosPcieDdiPtr;
-
-	ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-PCIe_PORT_DESCRIPTOR PortList[] = {
-		// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-		{
-			0,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
-		},
-		// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-			PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-		}
-};
-
-PCIe_DDI_DESCRIPTOR DdiList[] = {
-		// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-		{
-			DESCRIPTOR_TERMINATE_LIST,
-			PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-			//PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
-			{ConnectorTypeDP, Aux1, Hdp1}
-		},
-};
-
-PCIe_COMPLEX_DESCRIPTOR Brazos = {
-		DESCRIPTOR_TERMINATE_LIST,
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+	{
 		0,
-		&PortList[0],
-		&DdiList[0]
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+	}
 };
 
-	// GNB PCIe topology Porting
-
-	//
-	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	//
-	AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
-
-	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	ASSERT(Status == AGESA_SUCCESS);
-
-	BrazosPcieComplexListPtr	=	(PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(Brazos);
-	BrazosPciePortPtr		 =	(PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-	AllocHeapParams.BufferPtr += sizeof(PortList);
-	BrazosPcieDdiPtr			=	(PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-	memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
-	memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
-	memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
-
-
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =	(PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList	=	(PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = NULL,
+};
 
-	InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 	InitEarly->GnbConfig.PsppPolicy		= 0;
 }