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| author | Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> | 2020-06-18 12:30:42 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-07-02 19:32:43 +0000 |
| commit | 899b28acdb0f65521405540b7a52b2ad05049720 (patch) | |
| tree | 77a63cb12796f6859980f943bae88c61b44e03b1 | |
| parent | 43bcc7b6ed1502de80a857f94443f7c83269ad36 (diff) | |
| download | coreboot-899b28acdb0f65521405540b7a52b2ad05049720.tar.gz coreboot-899b28acdb0f65521405540b7a52b2ad05049720.tar.bz2 coreboot-899b28acdb0f65521405540b7a52b2ad05049720.zip | |
mb/pcengines/apu1/mainboard.c: reorder includes
Originally, there was problem with PC Engines apu1 platform
which returned serial number value as -64. It was caused by wrong
value of dev->bus->secondary.
Source of the problem is in Porting.h header file. It contains
'#pragma pack(1)' which affects struct device. As mainboard.c
uses different binary layout because of this attribute,
reference dev->bus->secondary lands at wrong memory address.
This patch reorder includes and put <AGESA.h> and <AMD.h>
at the end of list, making struct device consistent.
As a result bus number value in device's structure is correct
and hence serial number.
TEST=`dmidecode -t 2` command in Linux Debian
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Change-Id: I5e8690d100b38ac7889395d375c0ff32bdefda0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42512
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/pcengines/apu1/mainboard.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index a2a78c55ce8e..45d326a818e8 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpimmio.h> -#include <AGESA.h> -#include <AMD.h> + #include <console/console.h> #include <device/device.h> #include <device/mmio.h> @@ -11,12 +10,14 @@ #include <southbridge/amd/common/amd_pci_util.h> #include <smbios.h> #include <string.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/family14/pci_devs.h> #include <superio/nuvoton/nct5104d/nct5104d.h> #include "gpio_ftns.h" +#include <AGESA.h> +#include <AMD.h> +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -301,7 +302,7 @@ const char *smbios_mainboard_serial_number(void) /* Read in the last 3 bytes of NIC's MAC address. */ bar18 = pci_read_config32(dev, 0x18); - bar18 &= 0xFFFFFC00; + bar18 &= 0xFFFFFFF0; for (i = 3; i < 6; i++) { mac_addr <<= 8; mac_addr |= read8((u8 *)bar18 + i); |