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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-07-07 17:17:32 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-07-08 08:08:42 +0200 |
| commit | 8e3997552ac0483f2de56a5dcce093bbfb8cfd0b (patch) | |
| tree | fdd72159c59e2dfda290592770c65d19ab5b54db | |
| parent | 9eb61809638db2d6cf4068b8509c46a4632b925c (diff) | |
| download | coreboot-8e3997552ac0483f2de56a5dcce093bbfb8cfd0b.tar.gz coreboot-8e3997552ac0483f2de56a5dcce093bbfb8cfd0b.tar.bz2 coreboot-8e3997552ac0483f2de56a5dcce093bbfb8cfd0b.zip | |
memlayout: Add timestamp regions for t210 and cygnus
This is needed to make those SOCs compile with timestamps enabled.
Change-Id: Iac20cb9911e1c76a18c8530385c9d7b8b46399e5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10833
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
| -rw-r--r-- | src/soc/broadcom/cygnus/include/soc/memlayout.ld | 1 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/include/soc/memlayout.ld | 3 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld | 1 |
3 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld index 3f6e8d8298f4..5e149b4c4de7 100644 --- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld +++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld @@ -34,6 +34,7 @@ SECTIONS VBOOT2_WORK(0x02010000, 16K) OVERLAP_VERSTAGE_ROMSTAGE(0x02014000, 120K) PRERAM_CBFS_CACHE(0x02032000, 1K) + TIMESTAMP(0x02032400, 1K) STACK(0x02033000, 12K) REGION(reserved_for_secure_service_api, 0x0203F000, 4K, 4) SRAM_END(0x02040000) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index df9eed5ea19d..526fbbe6b918 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -34,7 +34,8 @@ SECTIONS PRERAM_CBMEM_CONSOLE(0x40000000, 8K) PRERAM_CBFS_CACHE(0x40002000, 84K) STACK(0x40017000, 16K) - BOOTBLOCK(0x4001B000, 26K) + TIMESTAMP(0x4001B000, 2K) + BOOTBLOCK(0x4001B800, 24K) ROMSTAGE(0x40022000, 120K) SRAM_END(0x40040000) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld index 5c8f3468c784..26c6e34c4ada 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld @@ -36,6 +36,7 @@ SECTIONS PRERAM_CBFS_CACHE(0x40002000, 72K) VBOOT2_WORK(0x40014000, 16K) STACK(0x40018000, 2K) + TIMESTAMP(0x40018800, 2K) BOOTBLOCK(0x40019000, 24K) VERSTAGE(0x4001F000, 52K) ROMSTAGE(0x4002C000, 80K) |