diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2024-06-06 19:12:41 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2024-06-09 18:47:52 +0000 |
| commit | 9058b46f9c095651a0a14c47a5be2e4f25ecdab2 (patch) | |
| tree | ae4406af76f523e1d0400c18a1256aead1dc784e | |
| parent | c2d967aaf9aab4498b5d09b85e8a5a0fb4bc46ac (diff) | |
| download | coreboot-9058b46f9c095651a0a14c47a5be2e4f25ecdab2.tar.gz coreboot-9058b46f9c095651a0a14c47a5be2e4f25ecdab2.tar.bz2 coreboot-9058b46f9c095651a0a14c47a5be2e4f25ecdab2.zip | |
sb/intel/lynxpoint/pcie.c: Add 9-series PCH-H device IDs
Looks like PCIe root port device IDs for 9-series PCH-H are missing from
commit 434d7d45829e (sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHs)
for some reason. Add them, so that coreboot performs PCIe initialisation
for 9-series PCH-H.
Change-Id: I1589418e5e25daabbf09c66c637e9c4f86aa02a6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82947
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/include/device/pci_ids.h | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 8 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 267cb3221f98..7c3b55ecdeaf 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3185,6 +3185,14 @@ #define PCI_DID_INTEL_LPT_H_PCIE_RP6 0x8c1a #define PCI_DID_INTEL_LPT_H_PCIE_RP7 0x8c1c #define PCI_DID_INTEL_LPT_H_PCIE_RP8 0x8c1e +#define PCI_DID_INTEL_LPT_H_PCIE_RP1_9 0x8c90 +#define PCI_DID_INTEL_LPT_H_PCIE_RP2_9 0x8c92 +#define PCI_DID_INTEL_LPT_H_PCIE_RP3_9 0x8c94 +#define PCI_DID_INTEL_LPT_H_PCIE_RP4_9 0x8c96 +#define PCI_DID_INTEL_LPT_H_PCIE_RP5_9 0x8c98 +#define PCI_DID_INTEL_LPT_H_PCIE_RP6_9 0x8c9a +#define PCI_DID_INTEL_LPT_H_PCIE_RP7_9 0x8c9c +#define PCI_DID_INTEL_LPT_H_PCIE_RP8_9 0x8c9e #define PCI_DID_INTEL_LPT_LP_PCIE_RP1 0x9c10 #define PCI_DID_INTEL_LPT_LP_PCIE_RP2 0x9c12 #define PCI_DID_INTEL_LPT_LP_PCIE_RP3 0x9c14 diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 766ed433d5d2..645ae7e5bb2a 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -754,6 +754,14 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LPT_H_PCIE_RP6, PCI_DID_INTEL_LPT_H_PCIE_RP7, PCI_DID_INTEL_LPT_H_PCIE_RP8, + PCI_DID_INTEL_LPT_H_PCIE_RP1_9, + PCI_DID_INTEL_LPT_H_PCIE_RP2_9, + PCI_DID_INTEL_LPT_H_PCIE_RP3_9, + PCI_DID_INTEL_LPT_H_PCIE_RP4_9, + PCI_DID_INTEL_LPT_H_PCIE_RP5_9, + PCI_DID_INTEL_LPT_H_PCIE_RP6_9, + PCI_DID_INTEL_LPT_H_PCIE_RP7_9, + PCI_DID_INTEL_LPT_H_PCIE_RP8_9, PCI_DID_INTEL_LPT_LP_PCIE_RP1, PCI_DID_INTEL_LPT_LP_PCIE_RP2, PCI_DID_INTEL_LPT_LP_PCIE_RP3, |