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| author | Won Chung <wonchung@google.com> | 2024-03-19 02:25:45 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-05-06 11:21:45 +0000 |
| commit | 9207621d23aefe7213ab1a764bd78402237e4e8f (patch) | |
| tree | 67e70e4335a3bf75b37304d6dce0b7abe7bde390 | |
| parent | ce04bf8c7fda2e992cb405c8b3ccb2895541f65d (diff) | |
| download | coreboot-9207621d23aefe7213ab1a764bd78402237e4e8f.tar.gz coreboot-9207621d23aefe7213ab1a764bd78402237e4e8f.tar.bz2 coreboot-9207621d23aefe7213ab1a764bd78402237e4e8f.zip | |
mb/google/brya: Fix mux_conn index used by ec/google/chromeec
Within ec_acpi.c, USB-C ports are iterated to be matched with
corresponding mux. The iteration happens from 0 to the number of USB-C
ports. Given iteration index i, the port with PLD group_token of (i+1)
is matched with mux_conn[i].
Mithrax and Felwinter devicetree matches conn1 to mux_conn[1] and conn2
to mux_conn[0]. However, conn1 is for usbX_port2 which has group_token
of 1 and conn2 is for usbX_port3 which has group_token of 2. Thus,
follow the convention to add conn1 to mux_conn[0] and conn2 to
mux_conn[1].
Otherwise, the kernel subsystem linking between Type C connector and USB
mux will be swapped.
BUG=b:329657774 b:121287022 b:321051330 b:204230406
TEST=emerge-${BOARD} coreboot then check ACPI table on DUT.
TEST=Manually check that usb-role-switches are mapped to the correct
port.
Attach USB 3 A to C cable from development machine to left port of
DUT.
Attach nothing to right-hand port.
usbpd lines are workaround for devices without firmware patch to
connect superspeed lines.
ectool usbpd 0 none
ectool usbpd 0 usb
ectool usbpd 1 none
ectool usbpd 1 usb
echo host > /sys/class/typec/port0/usb-role-switch/role (should
succeed)
echo host > /sys/class/typec/port1/usb-role-switch/role (should fail
as no cable attached)
Change-Id: I349682a6fe3fe4848e4e86d9c446530a31b35875
Signed-off-by: Won Chung <wonchung@google.com>, Emilie Roberts <hadrosaur@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81354
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Emilie Roberts <hadrosaur@google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/felwinter/overridetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/mithrax/overridetree.cb | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 16c44af69204..40cbe4e46e04 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -349,8 +349,8 @@ chip soc/intel/alderlake end device ref pch_espi on chip ec/google/chromeec - use conn1 as mux_conn[1] - use conn2 as mux_conn[0] + use conn1 as mux_conn[0] + use conn2 as mux_conn[1] device pnp 0c09.0 on end end end diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb index 49dfea867e8a..6075351b250f 100644 --- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb @@ -297,8 +297,8 @@ chip soc/intel/alderlake end device ref pch_espi on chip ec/google/chromeec - use conn1 as mux_conn[1] - use conn2 as mux_conn[0] + use conn1 as mux_conn[0] + use conn2 as mux_conn[1] device pnp 0c09.0 on end end end |