diff options
author | Gang Chen <gang.c.chen@intel.com> | 2022-11-05 02:23:53 +0800 |
---|---|---|
committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-05-16 20:55:05 +0000 |
commit | 921ddba69ee1513de162c2ea65018124de4c95f1 (patch) | |
tree | 42360ca402e38ebc727bb22f62efda07d17d5956 | |
parent | 6258093575d63e3219bd32400e4801263ce92842 (diff) | |
download | coreboot-921ddba69ee1513de162c2ea65018124de4c95f1.tar.gz coreboot-921ddba69ee1513de162c2ea65018124de4c95f1.tar.bz2 coreboot-921ddba69ee1513de162c2ea65018124de4c95f1.zip |
mb/intel/avenuecity_crb: Add GNR/SRF-AP 2S server board Avenue City
Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP
AP SoCs (Granite Rapids AP and Sierra Forest AP).
This patch initially sets the code set up as a compilation target
with GNR N-1 FSP, and with basic feature supports (Integrated IO
Controller (IIO) configuration, BMC, UART, HPET).
TEST=Build on intel/avenuecity CRB
Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
-rw-r--r-- | configs/builder/config.intel.crb.avc | 50 | ||||
-rw-r--r-- | src/mainboard/intel/avenuecity_crb/Kconfig | 37 | ||||
-rw-r--r-- | src/mainboard/intel/avenuecity_crb/Kconfig.name | 4 | ||||
-rw-r--r-- | src/mainboard/intel/avenuecity_crb/Makefile.mk | 6 | ||||
-rw-r--r-- | src/mainboard/intel/avenuecity_crb/board.fmd | 12 | ||||
-rw-r--r-- | src/mainboard/intel/avenuecity_crb/board_info.txt | 6 | ||||
-rw-r--r-- | src/mainboard/intel/avenuecity_crb/bootblock.c | 24 | ||||
-rw-r--r-- | src/mainboard/intel/avenuecity_crb/config/iio.c | 29 | ||||
-rw-r--r-- | src/mainboard/intel/avenuecity_crb/devicetree.cb | 37 | ||||
-rw-r--r-- | src/mainboard/intel/avenuecity_crb/dsdt.asl | 21 | ||||
-rw-r--r-- | src/mainboard/intel/avenuecity_crb/ramstage.c | 8 | ||||
-rw-r--r-- | src/mainboard/intel/avenuecity_crb/romstage.c | 49 |
12 files changed, 283 insertions, 0 deletions
diff --git a/configs/builder/config.intel.crb.avc b/configs/builder/config.intel.crb.avc new file mode 100644 index 000000000000..eadcaf2cd8c6 --- /dev/null +++ b/configs/builder/config.intel.crb.avc @@ -0,0 +1,50 @@ +# Type this in coreboot root directory to get a working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.avc + +# +# [RO] Board Configurations +# +CONFIG_VENDOR_INTEL=y +CONFIG_BOARD_INTEL_AVENUECITY_CRB=y + +CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y +CONFIG_CONFIGURABLE_RAMSTAGE=y + +CONFIG_NO_GFX_INIT=y + +CONFIG_HAVE_IFD_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_LINUX=y + +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_CONSOLE_SERIAL_115200=y + +# +# [RW] IFWI Ingredients +# +CONFIG_IFD_BIN_PATH="site-local/avenuecity/descriptor.bin" +CONFIG_CPU_UCODE_BINARIES="site-local/avenuecity/ucode.mcb" +CONFIG_FSP_T_FILE="site-local/avenuecity/Server_T.fd" +CONFIG_FSP_M_FILE="site-local/avenuecity/Server_M.fd" +CONFIG_FSP_S_FILE="site-local/avenuecity/Server_S.fd" +CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/" + +CONFIG_PAYLOAD_FILE="site-local/avenuecity/linuxboot_bzImage" +CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200" + +# +# [RW] Debug Settings +# +CONFIG_CONSOLE_POST=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y + +CONFIG_VERIFY_HOBS=y +CONFIG_DISPLAY_MTRRS=y + +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y + +CONFIG_HAVE_DEBUG_GPIO=y +CONFIG_DEBUG_GPIO=y diff --git a/src/mainboard/intel/avenuecity_crb/Kconfig b/src/mainboard/intel/avenuecity_crb/Kconfig new file mode 100644 index 000000000000..fff244e92eb7 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/Kconfig @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_INTEL_AVENUECITY_CRB + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select SOC_INTEL_GRANITERAPIDS + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + select IPMI_KCS + select IPMI_KCS_ROMSTAGE + select VPD + select OCP_VPD + select MEMORY_MAPPED_TPM + +config CARDBUS_PLUGIN_SUPPORT + bool + default n + +config MAINBOARD_DIR + string + default "intel/avenuecity_crb" + +config MAINBOARD_PART_NUMBER + string + default "Avenue City CRB" + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config DIMM_MAX + int + default 1 + +endif diff --git a/src/mainboard/intel/avenuecity_crb/Kconfig.name b/src/mainboard/intel/avenuecity_crb/Kconfig.name new file mode 100644 index 000000000000..f73d1d936ff3 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_INTEL_AVENUECITY_CRB + bool "Avenue City CRB" diff --git a/src/mainboard/intel/avenuecity_crb/Makefile.mk b/src/mainboard/intel/avenuecity_crb/Makefile.mk new file mode 100644 index 000000000000..2e1a74a45a59 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += romstage.c +romstage-y += config/iio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/intel/avenuecity_crb/board.fmd b/src/mainboard/intel/avenuecity_crb/board.fmd new file mode 100644 index 000000000000..df5bc059f414 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/board.fmd @@ -0,0 +1,12 @@ +FLASH@0xfc000000 64M { + SI_ALL 48M { + SI_DESC@0x0 0x1000 + } + SI_BIOS 16M { + RW_MRC_CACHE 0x10000 + FMAP 0x800 + RW_VPD(PRESERVE) 0x4000 + RO_VPD(PRESERVE) 0x4000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/intel/avenuecity_crb/board_info.txt b/src/mainboard/intel/avenuecity_crb/board_info.txt new file mode 100644 index 000000000000..2c502cfdf2b6 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Avenue City CRB +Category: eval +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/intel/avenuecity_crb/bootblock.c b/src/mainboard/intel/avenuecity_crb/bootblock.c new file mode 100644 index 000000000000..e68d874c900e --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/bootblock.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <intelblocks/lpc_lib.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define ASPEED_SIO_PORT 0x2E + +void bootblock_mainboard_early_init(void) +{ + /* Enable eSPI decoding for com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + lpc_io_setup_comm_a_b(); + lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F); + + if (CONFIG_UART_FOR_CONSOLE == 0) { + /* Setup superio com1 */ + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + } else + die("COMs other than COM1 not supported\n"); +} diff --git a/src/mainboard/intel/avenuecity_crb/config/iio.c b/src/mainboard/intel/avenuecity_crb/config/iio.c new file mode 100644 index 000000000000..117d604a2dc0 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/config/iio.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/iio.h> + +static const struct iio_pe_config iio_config_table[] = { + /* + * CB_IIO_BIFURCATE_x8x2x2x2x2 is first set to indicate how the IIO is bifurcated + * then port settings are listed accordingly. The minimal port elements are x2. + * If an x8 port is enabled, the neighboring 3 x2 port elements needs to be + * disabled. + */ + {_IIO_PE_CFG_STRUCT(0x0, PE0, CB_IIO_BIFURCATE_x8x2x2x2x2, PE_TYPE_PCIE) { + /* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */ + _IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x1), + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x2), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x3), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x4), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x5), + }}, +}; + +const struct iio_pe_config *get_iio_config_table(int *size) +{ + *size = ARRAY_SIZE(iio_config_table); + return iio_config_table; +} diff --git a/src/mainboard/intel/avenuecity_crb/devicetree.cb b/src/mainboard/intel/avenuecity_crb/devicetree.cb new file mode 100644 index 000000000000..0754916c393e --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/devicetree.cb @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/gnr + + # configure LPC generic IO decode ranges + # [bits 31..24: reserved] + # [bits 23..18: io decode address mask <7..2>] + # [bits 17..16: reserved] + # [bits 15..2 : io decode dword aligned address <15..2>] + # [bit 1 : reserved] + # [bit 0 : enabled] + register "gen1_dec" = "0x00000CA1" # IPMI KCS + + # configure FSP debug settings + register "serial_io_uart_debug_io_base" = CONFIG_TTYS0_BASE + + device domain 0 on + device pci 1f.0 on + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 # PNP_IDX_IO0 + irq 0x70 = 4 # PNP_IDX_IRQ0 + end + end + end + end + chip drivers/ipmi + device pnp ca2.0 on end # BMC KCS + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + end + end + end +end diff --git a/src/mainboard/intel/avenuecity_crb/dsdt.asl b/src/mainboard/intel/avenuecity_crb/dsdt.asl new file mode 100644 index 000000000000..34c29374faff --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/dsdt.asl @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/gnr/acpi/gpe.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <commonlib/include/commonlib/console/post_codes.h> + #include <arch/x86/acpi/post.asl> + #include <arch/x86/acpi/debug.asl> +} diff --git a/src/mainboard/intel/avenuecity_crb/ramstage.c b/src/mainboard/intel/avenuecity_crb/ramstage.c new file mode 100644 index 000000000000..a09016d46114 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + +} diff --git a/src/mainboard/intel/avenuecity_crb/romstage.c b/src/mainboard/intel/avenuecity_crb/romstage.c new file mode 100644 index 000000000000..9cd8cccadac7 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/romstage.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <drivers/ipmi/ipmi_if.h> +#include <drivers/ocp/include/vpd.h> +#include <drivers/vpd/vpd.h> +#include <fmap_config.h> +#include <device/device.h> +#include <soc/ddr.h> +#include <soc/iio.h> +#include <soc/romstage.h> +#include <string.h> + +#include "chip.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + /* FSP log outputs */ + const config_t *config = config_of_soc(); + m_cfg->SerialIoUartDebugIoBase = config->serial_io_uart_debug_io_base; + m_cfg->SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, FSP_LOG_DEFAULT); + m_cfg->DebugPrintLevel = config->debug_print_level; + m_cfg->serialDebugMsgLvl = get_int_from_vpd_range(FSP_MEM_LOG_LEVEL, + FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); + + /* Early connect BMC, e.g. to query configuration parameters */ + if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) + printk(BIOS_INFO, "IPMI at 0x%04x initialized successfully\n", + CONFIG_BMC_KCS_BASE); + + /* Set BIOS regeion UPD, otherwise MTRR might set incorrectly during TempRamExit API */ + m_cfg->BiosRegionBase = FMAP_SECTION_SI_BIOS_START; + m_cfg->BiosRegionSize = FMAP_SECTION_SI_BIOS_SIZE; + printk(BIOS_INFO, "BiosRegionBase is set to %x\n", mupd->FspmConfig.BiosRegionBase); + printk(BIOS_INFO, "BiosRegionSize is set to %x\n", mupd->FspmConfig.BiosRegionSize); + + /* IIO init */ + int size; + const struct iio_pe_config *iio_config_table = get_iio_config_table(&size); + soc_config_iio_pe_ports(mupd, iio_config_table, size); +} + +bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm) +{ + //TODO: not implemented yet + return false; +} |