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| author | Tim Crawford <tcrawford@system76.com> | 2022-11-28 09:30:23 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-02 14:30:51 +0000 |
| commit | 976050113e4f4505579ae3001c9ddf8eeeeaa572 (patch) | |
| tree | 8ef8160dc84ad53d5f5b45bdbc211f6f0dd6dc07 | |
| parent | fa2c118af49670b59c599d760a56f441a8bce71c (diff) | |
| download | coreboot-976050113e4f4505579ae3001c9ddf8eeeeaa572.tar.gz coreboot-976050113e4f4505579ae3001c9ddf8eeeeaa572.tar.bz2 coreboot-976050113e4f4505579ae3001c9ddf8eeeeaa572.zip | |
mb/system76/adl-p: Disable SATA DevSlp
After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0# in
system76/ec@cc3effb6a451 ("board/system76/common: use SLP_S0# pin for
modern standby detection"), DevSlp blocks suspend entry. Disable it
until it is fixed.
Change-Id: I586245ebf9f9d5ad08f6745a450411f194a661da
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
| -rw-r--r-- | src/mainboard/system76/adl-p/devicetree.cb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/system76/adl-p/devicetree.cb b/src/mainboard/system76/adl-p/devicetree.cb index 6a9f362ac9ac..c7085b448b79 100644 --- a/src/mainboard/system76/adl-p/devicetree.cb +++ b/src/mainboard/system76/adl-p/devicetree.cb @@ -73,7 +73,8 @@ chip soc/intel/alderlake device ref sata on register "sata_salp_support" = "1" register "sata_ports_enable[1]" = "1" # SSD1 - register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1) + # FIXME: DevSlp breaks S0ix + #register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1) end device ref pch_espi on register "gen1_dec" = "0x00040069" # EC PM channel |