diff options
author | Rob Barnes <robbarnes@google.com> | 2021-10-27 11:25:43 -0600 |
---|---|---|
committer | Karthik Ramasubramanian <kramasub@google.com> | 2021-10-27 23:23:05 +0000 |
commit | 9a56ff9c2d2657f1cf5c9c18e96caaddd7897f68 (patch) | |
tree | bc9e840841541308262f5ab93adfc42d66030daa | |
parent | b4182989d7f74e10633f136a3b176ddd803b2d8c (diff) | |
download | coreboot-9a56ff9c2d2657f1cf5c9c18e96caaddd7897f68.tar.gz coreboot-9a56ff9c2d2657f1cf5c9c18e96caaddd7897f68.tar.bz2 coreboot-9a56ff9c2d2657f1cf5c9c18e96caaddd7897f68.zip |
mb/google/guybrush: Move EN_PWR_FP from GPIO_32 to GPIO_3
EN_PWR_FP is used to enable power to the FPMCU. This frees up GPIO_32
for other uses.
This move applies to all board except:
* Guybrush
* Nipperkin board version 1
Add callbacks for variants to override fpmcu shtudown gpio table and
fpmcu disable gpio table.
BUG=b:202992077
TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure fingerprint
still works.
Change-Id: I4501554da0fab0cb35684735e7d1da6f20e255eb
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
6 files changed, 136 insertions, 24 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 94ed74cff558..89594faf4219 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -17,8 +17,8 @@ static const struct soc_amd_gpio base_gpio_table[] = { PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), /* WAKE_L */ PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), - /* Unused */ - PAD_NC(GPIO_3), + /* EN_PWR_FP */ + PAD_GPO(GPIO_3, HIGH), /* SOC_PEN_DETECT_ODL */ PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S0i3), /* SD_AUX_RESET_L */ @@ -68,8 +68,8 @@ static const struct soc_amd_gpio base_gpio_table[] = { PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* EN_SPKR */ PAD_GPO(GPIO_31, HIGH), - /* EN_PWR_FP */ - PAD_GPO(GPIO_32, HIGH), + /* Unused */ + PAD_NC(GPIO_32), /* GPIO_33 - GPIO_39: Not available */ /* SSD_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), @@ -291,11 +291,18 @@ static const struct soc_amd_gpio pcie_gpio_table[] = { PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), }; -static const struct soc_amd_gpio gpio_fp_shutdown_table[] = { +static const struct soc_amd_gpio fpmcu_shutdown_gpio_table[] = { /* FPMCU_RST_L */ PAD_GPO(GPIO_11, LOW), /* EN_PWR_FP */ - PAD_GPO(GPIO_32, LOW), + PAD_GPO(GPIO_3, LOW), +}; + +static const struct soc_amd_gpio fpmcu_disable_gpio_table[] = { + /* FPMCU_RST_L */ + PAD_NC(GPIO_11), + /* EN_PWR_FP */ + PAD_NC(GPIO_3), }; const struct soc_amd_gpio *__weak variant_pcie_gpio_table(size_t *size) @@ -348,37 +355,41 @@ const struct soc_amd_gpio *__weak variant_early_gpio_table(size_t *size) const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size) { - if (acpi_get_sleep_type() == ACPI_S5) { - *size = ARRAY_SIZE(gpio_fp_shutdown_table); - return gpio_fp_shutdown_table; - } + if (acpi_get_sleep_type() == ACPI_S5) + return variant_fpmcu_shutdown_gpio_table(size); *size = ARRAY_SIZE(sleep_gpio_table); return sleep_gpio_table; } +const __weak struct soc_amd_gpio *variant_fpmcu_shutdown_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(fpmcu_shutdown_gpio_table); + return fpmcu_shutdown_gpio_table; +} + +const __weak struct soc_amd_gpio *variant_fpmcu_disable_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(fpmcu_disable_gpio_table); + return fpmcu_disable_gpio_table; +} + __weak void variant_fpmcu_reset(void) { + size_t size; + const struct soc_amd_gpio *gpio_table; + if (acpi_get_sleep_type() == ACPI_S3) return; /* If the system is not resuming from S3, power off the FPMCU */ - static const struct soc_amd_gpio fpmcu_bootblock_table[] = { - /* SOC_FP_RST_L */ - PAD_GPO(GPIO_11, LOW), - /* EN_PWR_FP */ - PAD_GPO(GPIO_32, LOW), - }; - gpio_configure_pads(fpmcu_bootblock_table, ARRAY_SIZE(fpmcu_bootblock_table)); + gpio_table = variant_fpmcu_shutdown_gpio_table(&size); + gpio_configure_pads(gpio_table, size); } __weak void variant_finalize_gpios(void) { - static const struct soc_amd_gpio disable_fpmcu_table[] = { - /* FPMCU_RST_L */ - PAD_NC(GPIO_11), - /* EN_PWR_FP */ - PAD_NC(GPIO_32), - }; + size_t size; + const struct soc_amd_gpio *gpio_table; if (variant_has_fpmcu()) { if (acpi_get_sleep_type() == ACPI_S3) @@ -386,6 +397,7 @@ __weak void variant_finalize_gpios(void) /* Deassert the FPMCU reset to enable the FPMCU */ gpio_set(GPIO_11, 1); /* FPMCU_RST_L */ } else { - gpio_configure_pads(disable_fpmcu_table, ARRAY_SIZE(disable_fpmcu_table)); + gpio_table = variant_fpmcu_disable_gpio_table(&size); + gpio_configure_pads(gpio_table, size); } } diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 0fe0b3bae069..6cc96f84415a 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -40,6 +40,12 @@ const struct soc_amd_gpio *variant_pcie_gpio_table(size_t *size); /* This function provides GPIO settings before entering sleep. */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size); +/* This function provides GPIO settings for fpmcu shutdown. */ +const struct soc_amd_gpio *variant_fpmcu_shutdown_gpio_table(size_t *size); + +/* This function provides GPIO settings for fpmcu disable. */ +const struct soc_amd_gpio *variant_fpmcu_disable_gpio_table(size_t *size); + /* Finalize GPIOs, such as FPMCU power */ void variant_finalize_gpios(void); diff --git a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc index dd3b7754566e..fa2c4dec3854 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc @@ -12,3 +12,5 @@ ramstage-y += variant.c verstage-y += gpio.c subdirs-y += ./memory + +smm-y += gpio.c diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index 109ca0e018aa..4634c5a00e9e 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -23,6 +23,8 @@ static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = { PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* Unused */ PAD_NC(GPIO_85), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, HIGH), }; /* This table is used by guybrush variant with board version >= 2. */ @@ -35,6 +37,8 @@ static const struct soc_amd_gpio bid2_ramstage_gpio_table[] = { PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* Unused */ PAD_NC(GPIO_85), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, HIGH), }; static const struct soc_amd_gpio override_early_gpio_table[] = { @@ -63,6 +67,20 @@ static const struct soc_amd_gpio bid2_pcie_gpio_table[] = { PAD_GPO(GPIO_69, HIGH), }; +static const struct soc_amd_gpio fpmcu_shutdown_gpio_table[] = { + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + +static const struct soc_amd_gpio fpmcu_disable_gpio_table[] = { + /* FPMCU_RST_L */ + PAD_NC(GPIO_11), + /* EN_PWR_FP */ + PAD_NC(GPIO_32), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); @@ -100,3 +118,15 @@ const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) *size = ARRAY_SIZE(bid2_pcie_gpio_table); return bid2_pcie_gpio_table; } + +const struct soc_amd_gpio *variant_fpmcu_shutdown_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(fpmcu_shutdown_gpio_table); + return fpmcu_shutdown_gpio_table; +} + +const struct soc_amd_gpio *variant_fpmcu_disable_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(fpmcu_disable_gpio_table); + return fpmcu_disable_gpio_table; +} diff --git a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc index d6cd2623a28e..d7ec6dd5a232 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc @@ -12,3 +12,5 @@ ramstage-y += variant.c ramstage-y += ramstage.c subdirs-y += ./memory + +smm-y += gpio.c diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index 9a098dbb6634..6a12ad3a7059 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -22,6 +22,8 @@ static const struct soc_amd_gpio bid1_override_gpio_table[] = { PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* Unused */ PAD_NC(GPIO_85), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, HIGH), }; /* This table is used by nipperkin variant with board version >= 2. */ @@ -58,6 +60,38 @@ static const struct soc_amd_gpio bid2_override_pcie_gpio_table[] = { PAD_NC(GPIO_69), }; +/* This table is used by nipperkin variant with board version < 2. */ +static const struct soc_amd_gpio bid1_fpmcu_shutdown_gpio_table[] = { + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + +/* This table is used by nipperkin variant with board version >= 2. */ +static const struct soc_amd_gpio bid2_fpmcu_shutdown_gpio_table[] = { + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_3, LOW), +}; + +/* This table is used by nipperkin variant with board version < 2. */ +static const struct soc_amd_gpio bid1_fpmcu_disable_gpio_table[] = { + /* FPMCU_RST_L */ + PAD_NC(GPIO_11), + /* EN_PWR_FP */ + PAD_NC(GPIO_32), +}; + +/* This table is used by nipperkin variant with board version >= 2. */ +static const struct soc_amd_gpio bid2_fpmcu_disable_gpio_table[] = { + /* FPMCU_RST_L */ + PAD_NC(GPIO_11), + /* EN_PWR_FP */ + PAD_NC(GPIO_3), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); @@ -89,3 +123,29 @@ const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) *size = ARRAY_SIZE(bid2_override_pcie_gpio_table); return bid2_override_pcie_gpio_table; } + +const struct soc_amd_gpio *variant_fpmcu_shutdown_gpio_table(size_t *size) +{ + uint32_t board_version = board_id(); + + if (board_version < 2) { + *size = ARRAY_SIZE(bid1_fpmcu_shutdown_gpio_table); + return bid1_fpmcu_shutdown_gpio_table; + } + + *size = ARRAY_SIZE(bid2_fpmcu_shutdown_gpio_table); + return bid2_fpmcu_shutdown_gpio_table; +} + +const struct soc_amd_gpio *variant_fpmcu_disable_gpio_table(size_t *size) +{ + uint32_t board_version = board_id(); + + if (board_version < 2) { + *size = ARRAY_SIZE(bid1_fpmcu_disable_gpio_table); + return bid1_fpmcu_disable_gpio_table; + } + + *size = ARRAY_SIZE(bid2_fpmcu_disable_gpio_table); + return bid2_fpmcu_disable_gpio_table; +} |