Add Baytrail ChromeOS devices using variant scheme

Add new ChromeOS devices banjo, candy, clapper, glimmer, gnawty,
heli, kip, orco, quawks, squawks, sumo, swanky, and winky using
their common reference board (rambi) as a base.

Chromium sources used:
firmware-banjo-5216.334.B 32ec493 [chromeos: vboot_loader: Set...]
firmware-candy-5216.310.B 519ff11 [baytrail: Preserve VbNv around...]
firmware-clapper-5216.199.B 80d55e3 [baytrail: add code for...]
firmware-glimmer-5216.198.B fae0770 [baytrail: add code for...]
firmware-gnawty-5216.239.B 952adb7 [Gnawty/Olay: Add 2nd source...]
firmware-heli-5216.392.B f1f3604 [helis: Lock ME / TXE section...]
firmware-kip-5216.227.B db3c5d9 [kip: update spd for for MT41K256M16*]
firmware-orco-5216.362.B 76f1651 [Orco: Adjust rx delay for norm.]
firmware-quawks-5216.204.B edb60c9 [Quawks: Update SPD data]
firmware-squawks-5216.152.B c6573dc [Squawks: Update SPD data]
firmware-sumo-5216.382.B c62b6f23 [Ninja, Sumo: Add SPD source...]
firmware-swanky-5216.238.B 233b2a7 [Swanky: update SPD table]
firmware-winky-5216.265.B ce91ffc [Add to support HT Micron...]

The same basic cleanup/changes are made here as with the initial BYT
variant commit:
 - remove unused ACPI trackpad/touchscreen devices
 - correct I2C addresses in SMBIOS entries
 - clean up comment formatting
 - remove ACPI device for unused light sensor
 - switch I2C ACPI devices from edge to level triggered interrupts,
   for better compatibility/functionality (and to be consistent
   with other recently-upstreamed ChromeOS devices)
 - Micron 2GB SPD file for kip with updated values renamed to distinguish
   from same file used by other boards

Change-Id: Ic66f9b539afb5aff32c4c1a8563f6612f5a2927c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18164
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

114 files changed, 7263 insertions, 11 deletions

diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig
index a2bdc433ece7..128e6095770f 100644
--- a/src/mainboard/google/rambi/Kconfig
+++ b/src/mainboard/google/rambi/Kconfig
@@ -26,28 +26,80 @@ config MAINBOARD_DIR
 
 config VARIANT_DIR
 	string
+	default "banjo" if BOARD_GOOGLE_BANJO
+	default "candy" if BOARD_GOOGLE_CANDY
+	default "clapper" if BOARD_GOOGLE_CLAPPER
 	default "enguarde" if BOARD_GOOGLE_ENGUARDE
+	default "glimmer" if BOARD_GOOGLE_GLIMMER
+	default "gnawty" if BOARD_GOOGLE_GNAWTY
+	default "heli" if BOARD_GOOGLE_HELI
+	default "kip" if BOARD_GOOGLE_KIP
 	default "ninja" if BOARD_GOOGLE_NINJA
+	default "orco" if BOARD_GOOGLE_ORCO
+	default "quawks" if BOARD_GOOGLE_QUAWKS
 	default "rambi" if BOARD_GOOGLE_RAMBI
+	default "squawks" if BOARD_GOOGLE_SQUAWKS
+	default "sumo" if BOARD_GOOGLE_SUMO
+	default "swanky" if BOARD_GOOGLE_SWANKY
+	default "winky" if BOARD_GOOGLE_WINKY
 
 config MAINBOARD_PART_NUMBER
 	string
+	default "Banjo" if BOARD_GOOGLE_BANJO
+	default "Candy" if BOARD_GOOGLE_CANDY
+	default "Clapper" if BOARD_GOOGLE_CLAPPER
 	default "Enguarde" if BOARD_GOOGLE_ENGUARDE
+	default "Glimmer" if BOARD_GOOGLE_GLIMMER
+	default "Gnawty" if BOARD_GOOGLE_GNAWTY
+	default "Heli" if BOARD_GOOGLE_HELI
+	default "Kip" if BOARD_GOOGLE_KIP
 	default "Ninja" if BOARD_GOOGLE_NINJA
+	default "Orco" if BOARD_GOOGLE_ORCO
+	default "Quawks" if BOARD_GOOGLE_QUAWKS
 	default "Rambi" if BOARD_GOOGLE_RAMBI
+	default "Squawks" if BOARD_GOOGLE_SQUAWKS
+	default "Sumo" if BOARD_GOOGLE_SUMO
+	default "Swanky" if BOARD_GOOGLE_SWANKY
+	default "Winky" if BOARD_GOOGLE_WINKY
 
 config GBB_HWID
 	string
 	depends on CHROMEOS
+	default "BANJO TEST A-A 8843" if BOARD_GOOGLE_BANJO
+	default "CANDY TEST A-A 3347" if BOARD_GOOGLE_CANDY
+	default "CLAPPER TEST A-A 7705" if BOARD_GOOGLE_CLAPPER
 	default "ENGUARDE TEST A-A 0128" if BOARD_GOOGLE_ENGUARDE
+	default "GLIMMER TEST 8028" if BOARD_GOOGLE_GLIMMER
+	default "GNAWTY TEST A-A 3347" if BOARD_GOOGLE_GNAWTY
+	default "HELI TEST A-A 7705" if BOARD_GOOGLE_HELI
+	default "KIP TEST A-A 0128" if BOARD_GOOGLE_KIP
 	default "NINJA TEST A-A 0653" if BOARD_GOOGLE_NINJA
+	default "ORCO TEST 8028" if BOARD_GOOGLE_ORCO
+	default "QUAWKS TEST A-A 3347" if BOARD_GOOGLE_QUAWKS
 	default "RAMBI TEST A-A 0128" if BOARD_GOOGLE_RAMBI
+	default "SQUAWKS TEST A-A 7705" if BOARD_GOOGLE_SQUAWKS
+	default "SUMO TEST A-A 8843" if BOARD_GOOGLE_SUMO
+	default "SWANKY TEST A-A 0653" if BOARD_GOOGLE_SWANKY
+	default "WINKY TEST 0128" if BOARD_GOOGLE_WINKY
 
 config DEVICETREE
 	string
+	default "variants/banjo/devicetree.cb" if BOARD_GOOGLE_BANJO
+	default "variants/candy/devicetree.cb" if BOARD_GOOGLE_CANDY
+	default "variants/clapper/devicetree.cb" if BOARD_GOOGLE_CLAPPER
 	default "variants/enguarde/devicetree.cb" if BOARD_GOOGLE_ENGUARDE
+	default "variants/glimmer/devicetree.cb" if BOARD_GOOGLE_GLIMMER
+	default "variants/gnawty/devicetree.cb" if BOARD_GOOGLE_GNAWTY
+	default "variants/heli/devicetree.cb" if BOARD_GOOGLE_HELI
+	default "variants/kip/devicetree.cb" if BOARD_GOOGLE_KIP
 	default "variants/ninja/devicetree.cb" if BOARD_GOOGLE_NINJA
+	default "variants/orco/devicetree.cb" if BOARD_GOOGLE_ORCO
+	default "variants/quawks/devicetree.cb" if BOARD_GOOGLE_QUAWKS
 	default "variants/rambi/devicetree.cb" if BOARD_GOOGLE_RAMBI
+	default "variants/squawks/devicetree.cb" if BOARD_GOOGLE_SQUAWKS
+	default "variants/sumo/devicetree.cb" if BOARD_GOOGLE_SUMO
+	default "variants/swanky/devicetree.cb" if BOARD_GOOGLE_SWANKY
+	default "variants/winky/devicetree.cb" if BOARD_GOOGLE_WINKY
 
 config EC_GOOGLE_CHROMEEC_BOARDNAME
 	string
diff --git a/src/mainboard/google/rambi/Kconfig.name b/src/mainboard/google/rambi/Kconfig.name
index 0305bc424a5c..12cc3ff8f5c3 100644
--- a/src/mainboard/google/rambi/Kconfig.name
+++ b/src/mainboard/google/rambi/Kconfig.name
@@ -1,11 +1,63 @@
+config BOARD_GOOGLE_BANJO
+	bool "Banjo"
+	select BOARD_GOOGLE_BASEBOARD_RAMBI
+
+config BOARD_GOOGLE_CANDY
+	bool "Candy"
+	select BOARD_GOOGLE_BASEBOARD_RAMBI
+
+config BOARD_GOOGLE_CLAPPER
+	bool "Clapper"
+	select BOARD_GOOGLE_BASEBOARD_RAMBI
+
 config BOARD_GOOGLE_ENGUARDE
 	bool "Enguarde"
 	select BOARD_GOOGLE_BASEBOARD_RAMBI
 
+config BOARD_GOOGLE_GLIMMER
+	bool "Glimmer"
+	select BOARD_GOOGLE_BASEBOARD_RAMBI
+
+config BOARD_GOOGLE_GNAWTY
+	bool "Gnawty"
+	select BOARD_GOOGLE_BASEBOARD_RAMBI
+
+config BOARD_GOOGLE_HELI
+	bool "Heli"
+	select BOARD_GOOGLE_BASEBOARD_RAMBI
+
+config BOARD_GOOGLE_KIP
+	bool "Kip"
+	select BOARD_GOOGLE_BASEBOARD_RAMBI
+
 config BOARD_GOOGLE_NINJA
 	bool "Ninja"
 	select BOARD_GOOGLE_BASEBOARD_RAMBI
 
+config BOARD_GOOGLE_ORCO
+	bool "Orco"
+	select BOARD_GOOGLE_BASEBOARD_RAMBI
+
+config BOARD_GOOGLE_QUAWKS
+	bool "Quawks"
+	select BOARD_GOOGLE_BASEBOARD_RAMBI
+
+config BOARD_GOOGLE_SQUAWKS
+	bool "Squawks"
+	select BOARD_GOOGLE_BASEBOARD_RAMBI
+
 config BOARD_GOOGLE_RAMBI
 	bool "Rambi"
 	select BOARD_GOOGLE_BASEBOARD_RAMBI
+
+config BOARD_GOOGLE_SUMO
+	bool "Sumo"
+	select BOARD_GOOGLE_BASEBOARD_RAMBI
+
+config BOARD_GOOGLE_SWANKY
+	bool "Swanky"
+	select BOARD_GOOGLE_BASEBOARD_RAMBI
+
+config BOARD_GOOGLE_WINKY
+	bool "Winky"
+	select BOARD_GOOGLE_BASEBOARD_RAMBI
diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc
index b08002df1824..7c0fb35abf78 100644
--- a/src/mainboard/google/rambi/Makefile.inc
+++ b/src/mainboard/google/rambi/Makefile.inc
@@ -24,6 +24,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
 ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 
 ramstage-$(CONFIG_BOARD_GOOGLE_NINJA) += variants/$(VARIANT_DIR)/lan.c
+ramstage-$(CONFIG_BOARD_GOOGLE_SUMO) += variants/$(VARIANT_DIR)/lan.c
 
 subdirs-y += variants/$(VARIANT_DIR)
 
diff --git a/src/mainboard/google/rambi/acpi/touchscreen_amtel.asl b/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl
index 1aec3ce08328..1aec3ce08328 100644
--- a/src/mainboard/google/rambi/acpi/touchscreen_amtel.asl
+++ b/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl
diff --git a/src/mainboard/google/rambi/acpi/touchscreen_elan.asl b/src/mainboard/google/rambi/acpi/touchscreen_elan.asl
new file mode 100644
index 000000000000..ac0763d94709
--- /dev/null
+++ b/src/mainboard/google/rambi/acpi/touchscreen_elan.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <variant/onboard.h>
+
+Scope (\_SB.I2C6)
+{
+	Device (ETSA)
+	{
+		Name (_HID, "ELAN0001")
+		Name (_DDN, "ELAN Touchscreen")
+		Name (_UID, 1)
+		Name (ISTP, 0) /* TouchScreen */
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				BOARD_TOUCHSCREEN_I2C_ADDR,	// SlaveAddress
+				ControllerInitiated,		// SlaveMode
+				400000,				// ConnectionSpeed
+				AddressingMode7Bit,		// AddressingMode
+				"\\_SB.I2C6",			// ResourceSource
+			)
+			Interrupt (ResourceConsumer, Level, ActiveLow)
+			{
+				BOARD_TOUCHSCREEN_IRQ
+			}
+		})
+
+		Method (_STA)
+		{
+			If (LEqual (\S6EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+
+		/* Allow device to power off in S0 */
+		Name (_S0W, 4)
+	}
+}
diff --git a/src/mainboard/google/rambi/acpi/touchscreen_wdt.asl b/src/mainboard/google/rambi/acpi/touchscreen_wdt.asl
new file mode 100644
index 000000000000..0b5c100c7d53
--- /dev/null
+++ b/src/mainboard/google/rambi/acpi/touchscreen_wdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <variant/onboard.h>
+
+Scope (\_SB.I2C6)
+{
+	Device (WTSA)
+	{
+		Name (_HID, "WDHT0001")
+		Name (_DDN, "WDT Touchscreen")
+		Name (_UID, 6)
+		Name (ISTP, 0) /* TouchScreen */
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				BOARD_TOUCHSCREEN_I2C_ADDR,	// SlaveAddress
+				ControllerInitiated,		// SlaveMode
+				400000,				// ConnectionSpeed
+				AddressingMode7Bit,		// AddressingMode
+				"\\_SB.I2C6",			// ResourceSource
+			)
+			Interrupt (ResourceConsumer, Level, ActiveLow)
+			{
+				BOARD_TOUCHSCREEN_IRQ
+			}
+		})
+
+		Method (_STA)
+		{
+			If (LEqual (\S6EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+
+		/* Allow device to power off in S0 */
+		Name (_S0W, 4)
+	}
+}
diff --git a/src/mainboard/google/rambi/acpi/trackpad_amtel.asl b/src/mainboard/google/rambi/acpi/trackpad_atmel.asl
index 1d9fb461975b..1d9fb461975b 100644
--- a/src/mainboard/google/rambi/acpi/trackpad_amtel.asl
+++ b/src/mainboard/google/rambi/acpi/trackpad_atmel.asl
diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c
index eaf307938a81..acd4ffe090e1 100644
--- a/src/mainboard/google/rambi/mainboard.c
+++ b/src/mainboard/google/rambi/mainboard.c
@@ -129,7 +129,7 @@ static int int15_handler(void)
 static void mainboard_init(device_t dev)
 {
 	mainboard_ec_init();
-#if IS_ENABLED(CONFIG_BOARD_GOOGLE_NINJA)
+#if IS_ENABLED(CONFIG_BOARD_GOOGLE_NINJA) || IS_ENABLED(CONFIG_BOARD_GOOGLE_SUMO)
 	lan_init();
 #endif
 }
diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c
index 152d5e6c760b..d8ba001efac3 100644
--- a/src/mainboard/google/rambi/romstage.c
+++ b/src/mainboard/google/rambi/romstage.c
@@ -32,11 +32,15 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
 	ssus_disable_internal_pull(GPIO_SSUS_37_PAD);
 	ssus_disable_internal_pull(GPIO_SSUS_38_PAD);
 	ssus_disable_internal_pull(GPIO_SSUS_39_PAD);
-
+#ifdef GPIO_SSUS_40_PAD
+	ssus_disable_internal_pull(GPIO_SSUS_40_PAD);
+#endif
 	ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0);
 	ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1);
 	ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2);
-
+#ifdef GPIO_SSUS_40_PAD
+	ram_id |= (ssus_get_gpio(GPIO_SSUS_40_PAD) << 3);
+#endif
 	printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
 
 	if (ram_id >= total_spds)
diff --git a/src/mainboard/google/rambi/spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex b/src/mainboard/google/rambi/spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex
new file mode 100644
index 000000000000..19fa083b50d8
--- /dev/null
+++ b/src/mainboard/google/rambi/spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex
@@ -0,0 +1,32 @@
+92 13 0B 03 04 19 02 02
+03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81
+20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0F 11 40 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 07 92 01
+00 00 00 00 00 00 CC FB
+48 54 54 43 34 47 36 33
+43 46 52 2D 50 42 41 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/rambi/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/google/rambi/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
new file mode 100644
index 000000000000..8ced79063fcb
--- /dev/null
+++ b/src/mainboard/google/rambi/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
@@ -0,0 +1,17 @@
+# Hynix HMT425S6CFR6A-PBA
+92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0
+48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex
new file mode 100644
index 000000000000..ae1775633352
--- /dev/null
+++ b/src/mainboard/google/rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex
@@ -0,0 +1,32 @@
+92 12 0B 03 04 19 02 02
+03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81
+20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00
+00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0F 01 11 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01
+00 00 00 00 00 00 6C F9
+4B 34 42 34 47 31 36 34
+36 51 2D 48 59 4B 30 20
+20 20 00 00 80 CE 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex b/src/mainboard/google/rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex
new file mode 100644
index 000000000000..fc27f6b0181a
--- /dev/null
+++ b/src/mainboard/google/rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex
@@ -0,0 +1,32 @@
+92 12 0B 03 04 19 02 02
+03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81
+20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00
+00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0F 01 11 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01
+00 00 00 00 00 00 6C F9
+4D 34 37 31 42 35 36 37
+34 51 48 30 2D 59 4B 30
+20 20 00 00 80 CE 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/rambi/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex b/src/mainboard/google/rambi/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex
new file mode 100644
index 000000000000..6e3eab38290f
--- /dev/null
+++ b/src/mainboard/google/rambi/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex
@@ -0,0 +1,16 @@
+92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE
+45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46
+00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/rambi/spd/empty.spd.hex b/src/mainboard/google/rambi/spd/empty.spd.hex
new file mode 100644
index 000000000000..9ec39f1ba48c
--- /dev/null
+++ b/src/mainboard/google/rambi/spd/empty.spd.hex
@@ -0,0 +1,16 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex b/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex
new file mode 100644
index 000000000000..0e8c1bd99b45
--- /dev/null
+++ b/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex
@@ -0,0 +1,16 @@
+92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 22 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 96 77
+48 4D 54 34 32 35 53 36 4D 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex
new file mode 100644
index 000000000000..b8815c871279
--- /dev/null
+++ b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex
@@ -0,0 +1,32 @@
+92 13 0b 03 04 19 02 02
+03 11 01 08 09 00 fe 02
+69 78 69 30 69 11 10 79
+20 08 3c 3c 01 18 83 05
+00 00 ca 00 00 00 00 00
+00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 01 62 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 ec b8
+34 4b 54 46 32 35 36 36
+34 48 5a 2d 31 47 39 50
+31 20 50 32 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex
new file mode 100644
index 000000000000..91133b40509f
--- /dev/null
+++ b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex
@@ -0,0 +1,32 @@
+92 13 0b 03 04 19 02 02
+03 11 01 08 09 00 fe 02
+69 78 69 30 69 11 10 79
+20 08 3c 3c 01 18 83 05
+00 00 ca 00 00 00 00 00
+00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 01 62 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 45 1d
+34 4b 54 46 32 35 36 36
+34 48 5a 2d 31 47 39 50
+31 20 50 31 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex b/src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
new file mode 100644
index 000000000000..841291b23e33
--- /dev/null
+++ b/src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
@@ -0,0 +1,17 @@
+# Samsung K4B4G1646E-BYK0
+92 13 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 00 00 00 00 CA 0F
+4D 34 37 31 42 35 36 37 34 45 42 30 2D 59 4B 30
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/rambi/variants/banjo/Makefile.inc b/src/mainboard/google/rambi/variants/banjo/Makefile.inc
new file mode 100644
index 000000000000..e9252636ed18
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/banjo/Makefile.inc
@@ -0,0 +1,45 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b010 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b011 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b100 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+# 0b101 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/rambi/variants/banjo/devicetree.cb b/src/mainboard/google/rambi/variants/banjo/devicetree.cb
new file mode 100644
index 000000000000..e380920e0e92
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/banjo/devicetree.cb
@@ -0,0 +1,101 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Banjo board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x0"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 off end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 off end # I2C5
+		device pci 18.6 off end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 off  end # PCIE_PORT2
+		device pci 1c.2 off end # PCIE_PORT3
+		device pci 1c.3 off end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/rambi/variants/banjo/gpio.c b/src/mainboard/google/rambi/variants/banjo/gpio.c
new file mode 100644
index 000000000000..bfb2c9aa2f06
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/banjo/gpio.c
@@ -0,0 +1,229 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <mainboard/google/rambi/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_INPUT,	/* S0_NC07 - DDI1_DDCDATA - STRAP */
+	GPIO_NC,	/* S0_NC08 - NC */
+	GPIO_OUT_HIGH,	/* S0_NC09 - SOC_DISP_ON_C */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_FUNC2,	/* S0_SC001 - SATA_DEVSLP_C */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_NC,	/* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+	GPIO_FUNC1,	/* S0-SC004 - PCIE_CLKREQ_WLAN# */
+	GPIO_NC,	/* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+	GPIO_NC,	/* S0-SC006 - PCIE_CLKREQ3# (NC) */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_NC,	/* S0-SC033 - SD3_CLK */
+	GPIO_NC,	/* S0-SC034 - SD3_D0 */
+	GPIO_NC,	/* S0-SC035 - SD3_D1 */
+	GPIO_NC,	/* S0-SC036 - SD3_D2 */
+	GPIO_NC,	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_NC,	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_NC,	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_NC,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_NC,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_DIRQ,	/* S0-SC055 - TRACKPAD_INT_DX */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_INPUT,	/* S0-SC058 - SIM_DET_C */
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_NC,	/* S0-SC070 - ALS_INT_L - INT(NC) */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_DIRQ,	/* S0-SC072 - TOUCH_INT_L_DX */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_INPUT,	/* S0-SC076 - BIOS_STRAP - STRAP */
+	GPIO_INPUT,	/* S0-SC077 - SOC_OVERRIDE - STRAP */
+	GPIO_FUNC1,	/* S0-SC078 - I2C_0_SDA */
+	GPIO_FUNC1,	/* S0-SC079 - I2C_0_SCL */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_NC,	/* S0-SC086 - I2C_4_SDA */
+	GPIO_NC,	/* S0-SC087 - I2C_4_SCL */
+	GPIO_NC,	/* S0-SC088 - I2C_5_SDA */
+	GPIO_NC,	/* S0-SC089 - I2C_5_SCL */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_WAKE,	/* S500 - PCH_WAKE# */
+	GPIO_ACPI_WAKE,	/* S501 - TRACKPAD_INT# - INT */
+	GPIO_NC,	/* S502 - TOUCH_INT# - INT */
+	GPIO_FUNC6,	/* S503 - LTE_WAKE_L# - INT */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_FUNC1,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_NC,	/* S508 - NC */
+	GPIO_DIRQ,	/* S509 - MUX_AUD_INT1# */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_OUT_HIGH,	/* S535 - LTE_DISABLE_L */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_INPUT,	/* S537 - RAM_ID0 */
+	GPIO_INPUT,	/* S538 - RAM_ID1 */
+	GPIO_INPUT,	/* S539 - RAM_ID2 */
+	GPIO_NC,	/* S540 - NC */
+	GPIO_NC,	/* S541 - NC */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+	[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/dptf.asl
new file mode 100644
index 000000000000..4276b1cda5f4
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/dptf.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	90
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	45
+#define DPTF_TSR0_CRITICAL	80
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	46
+#define DPTF_TSR1_CRITICAL	75
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	44
+#define DPTF_TSR2_CRITICAL	75
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 },	/* 0.128A */
+})
diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl
new file mode 100644
index 000000000000..5a46bdc9e72c
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/mainboard.asl
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Elan trackpad */
+#include <mainboard/google/rambi/acpi/trackpad_elan.asl>
diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h b/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h
new file mode 100644
index 000000000000..38410e12f378
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/banjo/include/variant/onboard.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_IRQ              GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO        ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS          0
+#define BOARD_TRACKPAD_I2C_ADDR         0x15
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h b/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h
new file mode 100644
index 000000000000..a0134c04a13c
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b011 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b100 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+ * 0b101 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+*/
+
+static const uint32_t dual_channel_config =
+	(1 << 1) | (1 << 3) | (1 << 5);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/candy/Makefile.inc b/src/mainboard/google/rambi/variants/candy/Makefile.inc
new file mode 100644
index 000000000000..0a53d84cca41
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/candy/Makefile.inc
@@ -0,0 +1,58 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+# 0b0001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b0010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b0011 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b0100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+# 0b0101 - 2GiB total - 1 x 2GiB Hynix  H5TC2G63FFR-PBA 1600MHz
+# 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz
+# 0b0111 - 4GiB total - 2 x 2GiB Micron MT41K256M16TW-107 1600MHz
+# 0b1000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz
+# 0b1001 - 2GiB total - 1 x 2GiB Micron MT41K256M16TW-107 1600MHz
+# 0b1010 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+# 0b1011 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+
+SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0
+SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0
+SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/rambi/variants/candy/devicetree.cb b/src/mainboard/google/rambi/variants/candy/devicetree.cb
new file mode 100644
index 000000000000..5cbb974cb25e
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/candy/devicetree.cb
@@ -0,0 +1,102 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Candy board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+	register "usb2_comp_bg" = "0x4700"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 off end # I2C5
+		device pci 18.6 on  end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 off end # PCIE_PORT2
+		device pci 1c.2 off end # PCIE_PORT3
+		device pci 1c.3 off end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/rambi/variants/candy/gpio.c b/src/mainboard/google/rambi/variants/candy/gpio.c
new file mode 100644
index 000000000000..3cbfbaf45937
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/candy/gpio.c
@@ -0,0 +1,229 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <mainboard/google/rambi/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_INPUT,	/* S0_NC07 - DDI1_DDCDATA - STRAP */
+	GPIO_NC,	/* S0_NC08 - NC */
+	GPIO_OUT_HIGH,	/* S0_NC09 - SOC_DISP_ON_C */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_FUNC2,	/* S0_SC001 - SATA_DEVSLP_C */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_FUNC1,	/* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+	GPIO_FUNC1,	/* S0-SC004 - PCIE_CLKREQ_WLAN# */
+	GPIO_NC,	/* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+	GPIO_NC,	/* S0-SC006 - PCIE_CLKREQ3# (NC) */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_FUNC(1, PULL_DOWN, 20K),	/* S0-SC033 - SD3_CLK */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC034 - SD3_D0 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC035 - SD3_D1 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC036 - SD3_D2 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_NC,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_NC,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_DIRQ,	/* S0-SC055 - TRACKPAD_INT_DX */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_INPUT,	/* S0-SC058 - SIM_DET_C */
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_NC,	/* S0-SC070 - NC */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_DIRQ,	/* S0-SC072 - TOUCH_INT_L_DX */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_INPUT,	/* S0-SC076 - BIOS_STRAP - STRAP */
+	GPIO_INPUT,	/* S0-SC077 - SOC_OVERRIDE - STRAP */
+	GPIO_FUNC1,	/* S0-SC078 - I2C_0_SDA */
+	GPIO_FUNC1,	/* S0-SC079 - I2C_0_SCL */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_FUNC1,	/* S0-SC086 - I2C_4_SDA */
+	GPIO_FUNC1,	/* S0-SC087 - I2C_4_SCL */
+	GPIO_FUNC1,	/* S0-SC088 - I2C_5_SDA */
+	GPIO_FUNC1,	/* S0-SC089 - I2C_5_SCL */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_WAKE,	/* S500 - PCH_WAKE# */
+	GPIO_ACPI_WAKE,	/* S501 - TRACKPAD_INT# - INT */
+	GPIO_ACPI_WAKE,	/* S502 - TOUCH_INT# - INT */
+	GPIO_FUNC6,	/* S503 - LTE_WAKE_L# - INT */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_FUNC1,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_NC,	/* S508 - NC */
+	GPIO_DIRQ,	/* S509 - MUX_AUD_INT1# */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_OUT_HIGH,	/* S535 - LTE_DISABLE_L */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_INPUT,	/* S537 - RAM_ID0 */
+	GPIO_INPUT,	/* S538 - RAM_ID1 */
+	GPIO_INPUT,	/* S539 - RAM_ID2 */
+	GPIO_INPUT_PD_20K,	/* S540 - RAM_ID3 */
+	GPIO_NC,	/* S541 - NC */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+	[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/dptf.asl
new file mode 100644
index 000000000000..8dd08851a8db
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/dptf.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	85
+#define DPTF_CPU_CRITICAL	100
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	53
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	65
+#define DPTF_TSR1_CRITICAL	80
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	70
+#define DPTF_TSR2_CRITICAL	80
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 },	/* 0.128A */
+})
diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/mainboard.asl
new file mode 100644
index 000000000000..33d3209cd4aa
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/mainboard.asl
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Elan trackpad */
+#include <mainboard/google/rambi/acpi/trackpad_elan.asl>
+
+/* Elan touchscreen */
+#include <mainboard/google/rambi/acpi/touchscreen_elan.asl>
diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h b/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h
new file mode 100644
index 000000000000..9a6982123c7d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/candy/include/variant/onboard.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_IRQ              GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO        ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS          0
+#define BOARD_TRACKPAD_I2C_ADDR         0x15
+
+#define BOARD_TOUCHSCREEN_NAME          "touchscreen"
+#define BOARD_TOUCHSCREEN_IRQ           GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET)
+#define BOARD_TOUCHSCREEN_WAKE_GPIO     ACPI_ENABLE_WAKE_SUS_GPIO(2)
+#define BOARD_TOUCHSCREEN_I2C_BUS       5
+#define BOARD_TOUCHSCREEN_I2C_ADDR      0x10
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/variant.h b/src/mainboard/google/rambi/variants/candy/include/variant/variant.h
new file mode 100644
index 000000000000..0c58ceefa203
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/candy/include/variant/variant.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[3:0] are on GPIO_SSUS[40:37]
+ * 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b0001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b0010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b0011 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b0100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b0101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz
+ * 0b0111 - 4GiB total - 2 x 2GiB Micron MT41K256M16TW-107 1600MHz
+ * 0b1000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz
+ * 0b1001 - 2GiB total - 1 x 2GiB Micron MT41K256M16TW-107 1600MHz
+ * 0b1010 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+ * 0b1011 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+ */
+
+static const uint32_t dual_channel_config =
+	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7) | (1 << 10);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+#define GPIO_SSUS_40_PAD 52
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/clapper/Makefile.inc b/src/mainboard/google/rambi/variants/clapper/Makefile.inc
new file mode 100644
index 000000000000..1a01c8ae8669
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/clapper/Makefile.inc
@@ -0,0 +1,45 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+# 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+# 0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
+# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+# 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125
+SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA
+SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/rambi/variants/clapper/devicetree.cb b/src/mainboard/google/rambi/variants/clapper/devicetree.cb
new file mode 100644
index 000000000000..a95ddd144eec
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/clapper/devicetree.cb
@@ -0,0 +1,89 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Clapper board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "scc_acpi_mode" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "5"	# 400ms
+	register "gpu_pipea_power_on_delay" = "2000"	# 200ms
+	register "gpu_pipea_light_on_delay" = "10"	# 1ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 on  end # I2C5
+		device pci 18.6 on  end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 off end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 on  end # PCIE_PORT2
+		device pci 1c.2 off end # PCIE_PORT3
+		device pci 1c.3 off end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/rambi/variants/clapper/gpio.c b/src/mainboard/google/rambi/variants/clapper/gpio.c
new file mode 100644
index 000000000000..385b40627a9b
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/clapper/gpio.c
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <mainboard/google/rambi/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_INPUT,	/* S0_NC07 - DDI1_DDCDATA - STRAP */
+	GPIO_NC,	/* S0_NC08 - NC */
+	GPIO_FUNC2,	/* S0_NC09 - SOC_DISP_ON_C */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_FUNC2,	/* S0_SC001 - SATA_DEVSLP_C */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_FUNC1,	/* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+	GPIO_FUNC1,	/* S0-SC004 - PCIE_CLKREQ_WLAN# */
+	GPIO_NC,	/* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+	GPIO_NC,	/* S0-SC006 - PCIE_CLKREQ3# (NC) */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_FUNC(1, PULL_DOWN, 20K),	/* S0-SC033 - SD3_CLK */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC034 - SD3_D0 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC035 - SD3_D1 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC036 - SD3_D2 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_NC,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_NC,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_DIRQ,	/* S0-SC055 - TRACKPAD_INT_DX */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_INPUT,	/* S0-SC058 - SIM_DET_C */
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_INPUT,	/* S0-SC070 - ALS_INT_L - INT */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_DIRQ,	/* S0-SC072 - TOUCH_INT_L_DX */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_INPUT,	/* S0-SC076 - BIOS_STRAP - STRAP */
+	GPIO_INPUT,	/* S0-SC077 - SOC_OVERRIDE - STRAP */
+	GPIO_FUNC1,	/* S0-SC078 - I2C_0_SDA */
+	GPIO_FUNC1,	/* S0-SC079 - I2C_0_SCL */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_FUNC1,	/* S0-SC086 - I2C_4_SDA */
+	GPIO_FUNC1,	/* S0-SC087 - I2C_4_SCL */
+	GPIO_FUNC1,	/* S0-SC088 - I2C_5_SDA */
+	GPIO_FUNC1,	/* S0-SC089 - I2C_5_SCL */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S500 - PCH_WAKE# */
+	GPIO_FUNC6,	/* S501 - TRACKPAD_INT# - INT */
+	GPIO_FUNC6,	/* S502 - TOUCH_INT# - INT */
+	GPIO_FUNC6,	/* S503 - LTE_WAKE_L# - INT */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_FUNC1,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_NC,	/* S508 - NC */
+	GPIO_NC,	/* S509 - MUX_AUD_INT1# (NC) */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_OUT_HIGH,	/* S535 - LTE_DISABLE_L */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_FUNC0,	/* S537 - RAM_ID0 */
+	GPIO_FUNC0,	/* S538 - RAM_ID1 */
+	GPIO_FUNC0,	/* S539 - RAM_ID2 */
+	GPIO_NC,	/* S540 - NC */
+	GPIO_NC,	/* S541 - NC */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+	[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+};
+
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/dptf.asl
new file mode 100644
index 000000000000..53dd09c0f377
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/dptf.asl
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	40
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	45
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	35
+#define DPTF_TSR2_CRITICAL	70
+
+#undef DPTF_ENABLE_CHARGER
diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/mainboard.asl
new file mode 100644
index 000000000000..82510bd3599a
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/mainboard.asl
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Elan trackpad */
+#include <mainboard/google/rambi/acpi/trackpad_elan.asl>
+
+/* Atmel touchscreen */
+#include <mainboard/google/rambi/acpi/touchscreen_atmel.asl>
diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h b/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h
new file mode 100644
index 000000000000..016f65747fcd
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/clapper/include/variant/onboard.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_IRQ              GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO        1       /* GPSSUS1 */
+#define BOARD_TRACKPAD_I2C_BUS          0
+#define BOARD_TRACKPAD_I2C_ADDR         0x15
+
+#define BOARD_TOUCHSCREEN_NAME          "touchscreen"
+#define BOARD_TOUCHSCREEN_IRQ           GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET)
+#define BOARD_TOUCHSCREEN_WAKE_GPIO     2       /* GPSSUS2 */
+#define BOARD_TOUCHSCREEN_I2C_BUS       5
+#define BOARD_TOUCHSCREEN_I2C_ADDR      0x4a
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h b/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h
new file mode 100644
index 000000000000..38b156c7761d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+ * 0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
+ * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ */
+
+static const uint32_t dual_channel_config =
+	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl
index 772b4bac0634..3cdd5c0cb21d 100644
--- a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/mainboard.asl
@@ -12,7 +12,5 @@
  * GNU General Public License for more details.
  */
 
-#include <variant/onboard.h>
-
 /* Elan trackpad */
 #include <mainboard/google/rambi/acpi/trackpad_elan.asl>
diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h b/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h
index 147779485181..2a1045d39b63 100644
--- a/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h
+++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/onboard.h
@@ -31,6 +31,4 @@
 #define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
 #define BOARD_ALS_IRQ                   GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET)
 
-#define BOARD_ALS_I2C_ADDR         	0x44
-
 #endif
diff --git a/src/mainboard/google/rambi/variants/glimmer/Makefile.inc b/src/mainboard/google/rambi/variants/glimmer/Makefile.inc
new file mode 100644
index 000000000000..341f6d341746
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/glimmer/Makefile.inc
@@ -0,0 +1,55 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b0000 - 4GiB total - 2 x 2GiB Micron  MT41K256M16HA-125:E 1600MHz
+# 0b0001 - 4GiB total - 2 x 2GiB Hynix   H5TC4G63AFR-PBA 1600MHz
+# 0b0010 - 2GiB total - 2 x 1GiB Micron  MT41K128M16JT-125:K 1600MHz
+# 0b0011 - 2GiB total - 2 x 1GiB Hynix   H5TC2G63FFR-PBA 1600MHz
+# 0b0100 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz
+# 0b0101 - 2GiB total - 1 x 2GiB Hynix   H5TC4G63AFR-PBA 1600MHz
+# 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b0111 - 4GiB total - 2 x 2GiB Elpida  EDJ4216EFBG-GNL-F 1600MHz
+# 0b1000 - 2GiB total - 1 x 2GiB Micron  MT41K256M16HA-125:E 1600MHz
+# 0b1001 - 2GiB total - 1 x 2GiB Elpida  EDJ4216EFBG-GNL-F 1600MHz
+# 0b1010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125
+SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA
+SPD_SOURCES += samsung_1GiB_dimm_K4B2G1646Q-BYK0
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F
+SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb
new file mode 100644
index 000000000000..bf01cd983c40
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb
@@ -0,0 +1,98 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Glimmer board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 on  end # I2C5
+		device pci 18.6 on  end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 on  end # PCIE_PORT2
+		device pci 1c.2 off end # PCIE_PORT3
+		device pci 1c.3 off end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/rambi/variants/glimmer/gpio.c b/src/mainboard/google/rambi/variants/glimmer/gpio.c
new file mode 100644
index 000000000000..8cfe90ea041b
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/glimmer/gpio.c
@@ -0,0 +1,231 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <mainboard/google/rambi/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_INPUT,	/* S0_NC07 - DDI1_DDCDATA - STRAP */
+	GPIO_NC,	/* S0_NC08 - NC */
+	GPIO_OUT_HIGH,	/* S0_NC09 - SOC_DISP_ON_C */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_FUNC2,	/* S0_SC001 - SATA_DEVSLP_C */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_FUNC1,	/* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+	GPIO_FUNC1,	/* S0-SC004 - PCIE_CLKREQ_WLAN# */
+	GPIO_NC,	/* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+	GPIO_NC,	/* S0-SC006 - PCIE_CLKREQ3# (NC) */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_FUNC(1, PULL_DOWN, 20K),	/* S0-SC033 - SD3_CLK */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC034 - SD3_D0 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC035 - SD3_D1 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC036 - SD3_D2 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_NC,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_NC,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_DIRQ,	/* S0-SC055 - TRACKPAD_INT_DX */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_INPUT,	/* S0-SC058 - SIM_DET_C */
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_NC,	/* S0-SC070 - ALS_INT_L - INT (NC) */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_DIRQ,	/* S0-SC072 - TOUCH_INT_L_DX */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_INPUT,	/* S0-SC076 - BIOS_STRAP - STRAP */
+	GPIO_INPUT,	/* S0-SC077 - SOC_OVERRIDE - STRAP */
+	GPIO_FUNC1,	/* S0-SC078 - I2C_0_SDA */
+	GPIO_FUNC1,	/* S0-SC079 - I2C_0_SCL */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_FUNC1,	/* S0-SC086 - I2C_4_SDA */
+	GPIO_FUNC1,	/* S0-SC087 - I2C_4_SCL */
+	GPIO_FUNC1,	/* S0-SC088 - I2C_5_SDA */
+	GPIO_FUNC1,	/* S0-SC089 - I2C_5_SCL */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_WAKE,	/* S500 - PCH_WAKE# */
+	GPIO_ACPI_WAKE,	/* S501 - TRACKPAD_INT# - INT */
+	GPIO_ACPI_WAKE,	/* S502 - TOUCH_INT# - INT */
+	GPIO_FUNC6,	/* S503 - LTE_WAKE_L# - INT */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_FUNC1,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_NC,	/* S508 - NC */
+	GPIO_DIRQ,	/* S509 - MUX_AUD_INT1# */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_OUT_HIGH,	/* S535 - LTE_DISABLE_L */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_INPUT,	/* S537 - RAM_ID0 */
+	GPIO_INPUT,	/* S538 - RAM_ID1 */
+	GPIO_INPUT,	/* S539 - RAM_ID2 */
+	/* TODO(shawnn): Change to normal input once our old boards
+	 * are no longer in use. */
+	GPIO_FUNC(0, PULL_DOWN, 20K),	/* S540 - RAM_ID3 */
+	GPIO_NC,	/* S541 - NC */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+	[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/dptf.asl
new file mode 100644
index 000000000000..6e2630be3b73
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/dptf.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	90
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Power_Bottom"
+#define DPTF_TSR0_PASSIVE	75
+#define DPTF_TSR0_CRITICAL	80
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_RAM_bottom"
+#define DPTF_TSR1_PASSIVE	75
+#define DPTF_TSR1_CRITICAL	80
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	75
+#define DPTF_TSR2_CRITICAL	80
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x8ca, "mA", 0 }, /* 2.25A (MAX) */
+	Package () { 0, 0, 0, 0, 32, 0x7d0, "mA", 0 },  /* 2.0A */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },  /* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },  /* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },   /* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 },   /* 0.128A */
+})
diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/mainboard.asl
new file mode 100644
index 000000000000..82510bd3599a
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/mainboard.asl
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Elan trackpad */
+#include <mainboard/google/rambi/acpi/trackpad_elan.asl>
+
+/* Atmel touchscreen */
+#include <mainboard/google/rambi/acpi/touchscreen_atmel.asl>
diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h b/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h
new file mode 100644
index 000000000000..121da36f99bc
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/onboard.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_IRQ              GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO        ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS          0
+#define BOARD_TRACKPAD_I2C_ADDR         0x15
+
+#define BOARD_TOUCHSCREEN_NAME          "touchscreen"
+#define BOARD_TOUCHSCREEN_IRQ           GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET)
+#define BOARD_TOUCHSCREEN_WAKE_GPIO     ACPI_ENABLE_WAKE_SUS_GPIO(2)
+#define BOARD_TOUCHSCREEN_I2C_BUS       5
+#define BOARD_TOUCHSCREEN_I2C_ADDR      0x4a
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h b/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h
new file mode 100644
index 000000000000..0ea42c52e9d2
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b0000 - 4GiB total - 2 x 2GiB Micron  MT41K256M16HA-125:E 1600MHz
+ * 0b0001 - 4GiB total - 2 x 2GiB Hynix   H5TC4G63AFR-PBA 1600MHz
+ * 0b0010 - 2GiB total - 2 x 1GiB Micron  MT41K128M16JT-125:K 1600MHz
+ * 0b0011 - 2GiB total - 2 x 1GiB Hynix   H5TC2G63FFR-PBA 1600MHz
+ * 0b0100 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz
+ * 0b0101 - 2GiB total - 1 x 2GiB Hynix   H5TC4G63AFR-PBA 1600MHz
+ * 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b0111 - 4GiB total - 2 x 2GiB Elpida  EDJ4216EFBG-GNL-F 1600MHz
+ * 0b1000 - 2GiB total - 1 x 2GiB Micron  MT41K256M16HA-125:E 1600MHz
+ * 0b1001 - 2GiB total - 1 x 2GiB Elpida  EDJ4216EFBG-GNL-F 1600MHz
+ * 0b1010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ */
+
+static const uint32_t dual_channel_config =
+	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) |
+	(1 << 4) |	      (1 << 6) | (1 << 7);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+#define GPIO_SSUS_40_PAD 52
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/gnawty/Makefile.inc b/src/mainboard/google/rambi/variants/gnawty/Makefile.inc
new file mode 100644
index 000000000000..05fbc698d4b6
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/gnawty/Makefile.inc
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+# 0b011 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63MFR-PBA 1600MHz
+# 0b100 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+# 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b110 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+# 0b111 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63MFR-PBA 1600MHz
+SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63MFR-PBA
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63MFR-PBA
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb
new file mode 100644
index 000000000000..bb6fcadde8d7
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb
@@ -0,0 +1,101 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Gnawty board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 on  end # I2C5
+		device pci 18.6 on  end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 on  end # PCIE_PORT2
+		device pci 1c.2 off end # PCIE_PORT3
+		device pci 1c.3 off end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/rambi/variants/gnawty/gpio.c b/src/mainboard/google/rambi/variants/gnawty/gpio.c
new file mode 100644
index 000000000000..e79dc5a827aa
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/gnawty/gpio.c
@@ -0,0 +1,229 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <mainboard/google/rambi/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_INPUT,	/* S0_NC07 - DDI1_DDCDATA - STRAP */
+	GPIO_NC,	/* S0_NC08 - NC */
+	GPIO_OUT_HIGH,	/* S0_NC09 - SOC_DISP_ON_C */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_FUNC2,	/* S0_SC001 - SATA_DEVSLP_C */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_FUNC1,	/* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+	GPIO_FUNC1,	/* S0-SC004 - PCIE_CLKREQ_WLAN# */
+	GPIO_NC,	/* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+	GPIO_NC,	/* S0-SC006 - PCIE_CLKREQ3# (NC) */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_FUNC(1, PULL_DOWN, 20K),	/* S0-SC033 - SD3_CLK */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC034 - SD3_D0 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC035 - SD3_D1 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC036 - SD3_D2 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_NC,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_NC,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_DIRQ,	/* S0-SC055 - TRACKPAD_INT_DX */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_INPUT,	/* S0-SC058 - SIM_DET_C */
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_NC,	/* S0-SC070 - ALS_INT_L - INT(NC) */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_DIRQ,	/* S0-SC072 - TOUCH_INT_L_DX */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_INPUT,	/* S0-SC076 - BIOS_STRAP - STRAP */
+	GPIO_INPUT,	/* S0-SC077 - SOC_OVERRIDE - STRAP */
+	GPIO_FUNC1,	/* S0-SC078 - I2C_0_SDA */
+	GPIO_FUNC1,	/* S0-SC079 - I2C_0_SCL */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_FUNC1,	/* S0-SC086 - I2C_4_SDA */
+	GPIO_FUNC1,	/* S0-SC087 - I2C_4_SCL */
+	GPIO_FUNC1,	/* S0-SC088 - I2C_5_SDA */
+	GPIO_FUNC1,	/* S0-SC089 - I2C_5_SCL */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_WAKE,	/* S500 - PCH_WAKE# */
+	GPIO_ACPI_WAKE,	/* S501 - TRACKPAD_INT# - INT */
+	GPIO_ACPI_WAKE,	/* S502 - TOUCH_INT# - INT */
+	GPIO_FUNC6,	/* S503 - LTE_WAKE_L# - INT */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_FUNC1,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_NC,	/* S508 - NC */
+	GPIO_DIRQ,	/* S509 - MUX_AUD_INT1# */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_OUT_HIGH,	/* S535 - LTE_DISABLE_L */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_INPUT,	/* S537 - RAM_ID0 */
+	GPIO_INPUT,	/* S538 - RAM_ID1 */
+	GPIO_INPUT,	/* S539 - RAM_ID2 */
+	GPIO_NC,	/* S540 - NC */
+	GPIO_NC,	/* S541 - NC */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+	[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/dptf.asl
new file mode 100644
index 000000000000..1df96fab959b
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/dptf.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	90
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	45
+#define DPTF_TSR0_CRITICAL	80
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	70
+#define DPTF_TSR1_CRITICAL	85
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	44
+#define DPTF_TSR2_CRITICAL	75
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 },	/* 0.128A */
+})
diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/mainboard.asl
new file mode 100644
index 000000000000..3cdd5c0cb21d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/mainboard.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Elan trackpad */
+#include <mainboard/google/rambi/acpi/trackpad_elan.asl>
diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h b/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h
new file mode 100644
index 000000000000..86ca488f3c70
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/onboard.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_IRQ              GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO        ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS          0
+#define BOARD_TRACKPAD_I2C_ADDR         0x15
+
+#define BOARD_TOUCHSCREEN_NAME          "touchscreen"
+#define BOARD_TOUCHSCREEN_IRQ           GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET)
+#define BOARD_TOUCHSCREEN_WAKE_GPIO     ACPI_ENABLE_WAKE_SUS_GPIO(2)
+#define BOARD_TOUCHSCREEN_I2C_BUS       5
+#define BOARD_TOUCHSCREEN_I2C_ADDR      0x10
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h b/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h
new file mode 100644
index 000000000000..9bac7bc89ead
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+ * 0b011 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63MFR-PBA 1600MHz
+ * 0b100 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+ * 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b110 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+ * 0b111 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63MFR-PBA 1600MHz
+*/
+
+static const uint32_t dual_channel_config =
+	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/heli/Makefile.inc b/src/mainboard/google/rambi/variants/heli/Makefile.inc
new file mode 100644
index 000000000000..d76a1274edae
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/heli/Makefile.inc
@@ -0,0 +1,55 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# RAM_ID	Vendor	Vendor_PN	Freq	Size	Total_size	channel
+# 0b0011	Hynix	H5TC4G63AFR-PBA	1600MHZ	4Gb	2GB	single-channel
+# 0b0100	Hynix	H5TC4G63CFR-PBA	1600MHZ	4Gb	2GB	single-channel
+# 0b0101	Samsung	K4B4G1646Q-HYK0	1600MHZ	4Gb	2GB	single-channel
+# 0b0110	Hynix	H5TC4G63CFR-PBA	1600MHZ	4Gb	4GB	dual-channel
+# 0b0111	Samsung	K4B4G1646Q-HYK0	1600MHZ	4Gb	4GB	dual-channel
+SPD_SOURCES = empty					# 0b0000
+SPD_SOURCES += empty					# 0b0001
+SPD_SOURCES += empty					# 0b0010
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA		# 0b0011
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA		# 0b0100
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0	# 0b0101
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA		# 0b0110
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0	# 0b0111
+SPD_SOURCES += empty					# 0b1000
+SPD_SOURCES += empty					# 0b1001
+SPD_SOURCES += empty					# 0b1010
+SPD_SOURCES += empty					# 0b1011
+SPD_SOURCES += empty					# 0b1100
+SPD_SOURCES += empty					# 0b1101
+SPD_SOURCES += empty					# 0b1110
+SPD_SOURCES += empty					# 0b1111
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/rambi/variants/heli/devicetree.cb b/src/mainboard/google/rambi/variants/heli/devicetree.cb
new file mode 100644
index 000000000000..d9b27e686630
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/heli/devicetree.cb
@@ -0,0 +1,102 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Heli board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+	register "usb2_comp_bg" = "0x4700"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 off  end # I2C5
+		device pci 18.6 off  end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 on  end # PCIE_PORT2
+		device pci 1c.2 off end # PCIE_PORT3
+		device pci 1c.3 off end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/rambi/variants/heli/gpio.c b/src/mainboard/google/rambi/variants/heli/gpio.c
new file mode 100644
index 000000000000..2a61c556cb34
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/heli/gpio.c
@@ -0,0 +1,228 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <mainboard/google/rambi/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_INPUT,	/* S0_NC07 - DDI1_DDCDATA - STRAP */
+	GPIO_NC,	/* S0_NC08 - NC */
+	GPIO_OUT_HIGH,	/* S0_NC09 - SOC_DISP_ON_C */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_FUNC2,	/* S0_SC001 - SATA_DEVSLP_C */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_FUNC1,	/* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+	GPIO_FUNC1,	/* S0-SC004 - PCIE_CLKREQ_WLAN# */
+	GPIO_NC,	/* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+	GPIO_NC,	/* S0-SC006 - PCIE_CLKREQ3# (NC) */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_FUNC(1, PULL_DOWN, 20K),	/* S0-SC033 - SD3_CLK */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC034 - SD3_D0 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC035 - SD3_D1 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC036 - SD3_D2 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_NC,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_NC,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_DIRQ,	/* S0-SC055 - TRACKPAD_INT_DX */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_NC,	/* S0-SC058 - SIM_DET_C (NC)*/
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_NC,	/* S0-SC070 - ALS_INT_L (NC) */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_NC,	/* S0-SC072 - TOUCH_INT_L_DX (NC) */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_INPUT,	/* S0-SC076 - BIOS_STRAP - STRAP */
+	GPIO_INPUT,	/* S0-SC077 - SOC_OVERRIDE - STRAP */
+	GPIO_FUNC1,	/* S0-SC078 - I2C_0_SDA */
+	GPIO_FUNC1,	/* S0-SC079 - I2C_0_SCL */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_FUNC1,	/* S0-SC086 - I2C_4_SDA */
+	GPIO_FUNC1,	/* S0-SC087 - I2C_4_SCL */
+	GPIO_FUNC1,	/* S0-SC088 - I2C_5_SDA */
+	GPIO_FUNC1,	/* S0-SC089 - I2C_5_SCL */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_WAKE,	/* S500 - PCH_WAKE# */
+	GPIO_ACPI_WAKE,	/* S501 - TRACKPAD_INT# - INT */
+	GPIO_NC,	/* S502 - TOUCH_INT# (NC) */
+	GPIO_NC,	/* S503 - LTE_WAKE_L# (NC) */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_NC,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_NC,	/* S508 - NC */
+	GPIO_DIRQ,	/* S509 - MUX_AUD_INT1# */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_NC,	/* S535 - LTE_DISABLE_L (NC) */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_INPUT,	/* S537 - RAM_ID0 */
+	GPIO_INPUT,	/* S538 - RAM_ID1 */
+	GPIO_INPUT,	/* S539 - RAM_ID2 */
+	GPIO_INPUT,	/* S540 - RAM_ID3 */
+	GPIO_NC,	/* S541 - NC */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/dptf.asl
new file mode 100644
index 000000000000..adc796d0e6c2
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/dptf.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	90
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	52
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	60
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	65
+#define DPTF_TSR2_CRITICAL	70
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 },	/* 0.128A */
+})
diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/mainboard.asl
new file mode 100644
index 000000000000..3cdd5c0cb21d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/mainboard.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Elan trackpad */
+#include <mainboard/google/rambi/acpi/trackpad_elan.asl>
diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h b/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h
new file mode 100644
index 000000000000..f4ffed5e6121
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/heli/include/variant/onboard.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_IRQ              GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO        ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS          0
+#define BOARD_TRACKPAD_I2C_ADDR         0x15
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/variant.h b/src/mainboard/google/rambi/variants/heli/include/variant/variant.h
new file mode 100644
index 000000000000..d25b9c9f214a
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/heli/include/variant/variant.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[3:0] are on GPIO_SSUS[40:37]
+ * RAM_ID	Vendor	Vendor_PN	Freq	Size	Total_size	channel
+ * 0b0011	Hynix	H5TC4G63AFR-PBA	1600MHZ	4Gb	2GB	single-channel
+ * 0b0100	Hynix	H5TC4G63CFR-PBA	1600MHZ	4Gb	2GB	single-channel
+ * 0b0101	Samsung	K4B4G1646Q-HYK0	1600MHZ	4Gb	2GB	single-channel
+ * 0b0110	Hynix	H5TC4G63CFR-PBA	1600MHZ	4Gb	4GB	dual-channel
+ * 0b0111	Samsung	K4B4G1646Q-HYK0	1600MHZ	4Gb	4GB	dual-channel
+ */
+
+static const uint32_t dual_channel_config =
+	(1 << 6) | (1 << 7);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+#define GPIO_SSUS_40_PAD 52
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/kip/Makefile.inc b/src/mainboard/google/rambi/variants/kip/Makefile.inc
new file mode 100644
index 000000000000..06bd0e738aba
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/kip/Makefile.inc
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 4GiB total - 2 x 2GiB Micron  MT41K256M16HA-125:E 1600MHz
+# 0b001 - 4GiB total - 2 x 2GiB Hynix   H5TC4G63AFR-PBA 1600MHz
+# 0b010 - 4GiB total - 2 x 2GiB Elpida  EDJ4216EFBG-GNL-F 1600MHz
+# 0b011 - 2GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b100 - 2GiB total - 1 x 2GiB Micron  MT41K256M16HA-125:E 1600MHz
+# 0b101 - 2GiB total - 1 x 2GiB Hynix   H5TC4G63AFR-PBA 1600MHz
+# 0b110 - 2GiB total - 1 x 2GiB Elpida  EDJ4216EFBG-GNL-F 1600MHz
+# 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125a
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125a
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/rambi/variants/kip/devicetree.cb b/src/mainboard/google/rambi/variants/kip/devicetree.cb
new file mode 100644
index 000000000000..f4e0a9173a9c
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/kip/devicetree.cb
@@ -0,0 +1,101 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Kip board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 on  end # I2C5
+		device pci 18.6 off end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 on  end # PCIE_PORT2
+		device pci 1c.2 off end # PCIE_PORT3
+		device pci 1c.3 off end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/rambi/variants/kip/gpio.c b/src/mainboard/google/rambi/variants/kip/gpio.c
new file mode 100644
index 000000000000..3d79d374412d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/kip/gpio.c
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <mainboard/google/rambi/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_INPUT,	/* S0_NC07 - DDI1_DDCDATA - STRAP */
+	GPIO_NC,	/* S0_NC08 - NC */
+	GPIO_OUT_HIGH,	/* S0_NC09 - SOC_DISP_ON_C */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_FUNC2,	/* S0_SC001 - SATA_DEVSLP_C */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_FUNC1,	/* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+	GPIO_FUNC1,	/* S0-SC004 - PCIE_CLKREQ_WLAN# */
+	GPIO_NC,	/* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+	GPIO_NC,	/* S0-SC006 - PCIE_CLKREQ3# (NC) */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_FUNC(1, PULL_DOWN, 20K),	/* S0-SC033 - SD3_CLK */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC034 - SD3_D0 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC035 - SD3_D1 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC036 - SD3_D2 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_NC,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_NC,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_DIRQ,	/* S0-SC055 - TRACKPAD_INT_DX */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_INPUT,	/* S0-SC058 - SIM_DET_C */
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_DIRQ,	/* S0-SC070 - ALS_INT_L - INT */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_DIRQ,	/* S0-SC072 - TOUCH_INT_L_DX */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_INPUT,	/* S0-SC076 - BIOS_STRAP - STRAP */
+	GPIO_INPUT,	/* S0-SC077 - SOC_OVERRIDE - STRAP */
+	GPIO_FUNC1,	/* S0-SC078 - I2C_0_SDA */
+	GPIO_FUNC1,	/* S0-SC079 - I2C_0_SCL */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_FUNC1,	/* S0-SC086 - I2C_4_SDA */
+	GPIO_FUNC1,	/* S0-SC087 - I2C_4_SCL */
+	GPIO_FUNC1,	/* S0-SC088 - I2C_5_SDA */
+	GPIO_FUNC1,	/* S0-SC089 - I2C_5_SCL */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_WAKE,	/* S500 - PCH_WAKE# */
+	GPIO_ACPI_WAKE,	/* S501 - TRACKPAD_INT# - INT */
+	GPIO_ACPI_WAKE,	/* S502 - TOUCH_INT# - INT */
+	GPIO_FUNC6,	/* S503 - LTE_WAKE_L# - INT */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_FUNC1,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_NC,	/* S508 - NC */
+	GPIO_DIRQ,	/* S509 - MUX_AUD_INT1# */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_OUT_HIGH,	/* S535 - LTE_DISABLE_L */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_INPUT,	/* S537 - RAM_ID0 */
+	GPIO_INPUT,	/* S538 - RAM_ID1 */
+	GPIO_INPUT,	/* S539 - RAM_ID2 */
+	GPIO_NC,	/* S540 - NC */
+	GPIO_NC,	/* S541 - NC */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+	[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+	[ALS_IRQ_OFFSET] = ALS_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/dptf.asl
new file mode 100644
index 000000000000..e88ac7df426d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/dptf.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	90
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	58
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	58
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	57
+#define DPTF_TSR2_CRITICAL	70
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 },	/* 0.128A */
+})
diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/mainboard.asl
new file mode 100644
index 000000000000..3cdd5c0cb21d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/mainboard.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Elan trackpad */
+#include <mainboard/google/rambi/acpi/trackpad_elan.asl>
diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h b/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h
new file mode 100644
index 000000000000..4bb37be51c8c
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/kip/include/variant/onboard.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_IRQ              GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO        ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS          0
+#define BOARD_TRACKPAD_I2C_ADDR         0x15
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+#define BOARD_ALS_IRQ                   GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/variant.h b/src/mainboard/google/rambi/variants/kip/include/variant/variant.h
new file mode 100644
index 000000000000..7f058d7ccb17
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/kip/include/variant/variant.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 4GiB total - 2 x 2GiB Micron  MT41K256M16HA-125:E 1600MHz
+ * 0b001 - 4GiB total - 2 x 2GiB Hynix   H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 4GiB total - 2 x 2GiB Elpida  EDJ4216EFBG-GNL-F 1600MHz
+ * 0b011 - 2GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b100 - 2GiB total - 1 x 2GiB Micron  MT41K256M16HA-125:E 1600MHz
+ * 0b101 - 2GiB total - 1 x 2GiB Hynix   H5TC4G63AFR-PBA 1600MHz
+ * 0b110 - 2GiB total - 1 x 2GiB Elpida  EDJ4216EFBG-GNL-F 1600MHz
+ * 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ */
+
+static const uint32_t dual_channel_config =
+	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/orco/Makefile.inc b/src/mainboard/google/rambi/variants/orco/Makefile.inc
new file mode 100644
index 000000000000..1f9706e19229
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/orco/Makefile.inc
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+# 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+# 0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
+# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+# 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125
+SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA
+SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/rambi/variants/orco/devicetree.cb b/src/mainboard/google/rambi/variants/orco/devicetree.cb
new file mode 100644
index 000000000000..829179462ffc
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/orco/devicetree.cb
@@ -0,0 +1,101 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Orco board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 off end # I2C5
+		device pci 18.6 off end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 on  end # PCIE_PORT2
+		device pci 1c.2 off end # PCIE_PORT3
+		device pci 1c.3 off end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/rambi/variants/orco/gpio.c b/src/mainboard/google/rambi/variants/orco/gpio.c
new file mode 100644
index 000000000000..f2bbe8abdb9e
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/orco/gpio.c
@@ -0,0 +1,229 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <mainboard/google/rambi/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_INPUT,	/* S0_NC07 - DDI1_DDCDATA - STRAP */
+	GPIO_NC,	/* S0_NC08 - NC */
+	GPIO_OUT_HIGH,	/* S0_NC09 - SOC_DISP_ON_C */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_FUNC2,	/* S0_SC001 - SATA_DEVSLP_C */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_FUNC1,	/* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+	GPIO_FUNC1,	/* S0-SC004 - PCIE_CLKREQ_WLAN# */
+	GPIO_NC,	/* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+	GPIO_NC,	/* S0-SC006 - PCIE_CLKREQ3# (NC) */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_FUNC(1, PULL_DOWN, 20K),	/* S0-SC033 - SD3_CLK */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC034 - SD3_D0 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC035 - SD3_D1 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC036 - SD3_D2 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_NC,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_NC,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_DIRQ,	/* S0-SC055 - TRACKPAD_INT_DX */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_INPUT,	/* S0-SC058 - SIM_DET_C */
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_NC,	/* S0-SC070 - ALS_INT_L - INT (NC) */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_DIRQ,	/* S0-SC072 - TOUCH_INT_L_DX */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_INPUT,	/* S0-SC076 - BIOS_STRAP - STRAP */
+	GPIO_INPUT,	/* S0-SC077 - SOC_OVERRIDE - STRAP */
+	GPIO_FUNC1,	/* S0-SC078 - I2C_0_SDA */
+	GPIO_FUNC1,	/* S0-SC079 - I2C_0_SCL */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_NC,	/* S0-SC086 - I2C_4_SDA */
+	GPIO_NC,	/* S0-SC087 - I2C_4_SCL */
+	GPIO_NC,	/* S0-SC088 - I2C_5_SDA */
+	GPIO_NC,	/* S0-SC089 - I2C_5_SCL */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_WAKE,	/* S500 - PCH_WAKE# */
+	GPIO_ACPI_WAKE,	/* S501 - TRACKPAD_INT# - INT */
+	GPIO_NC,	/* S502 - TOUCH_INT# - INT */
+	GPIO_NC,	/* S503 - LTE_WAKE_L# - INT */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_NC,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_NC,	/* S508 - NC */
+	GPIO_DIRQ,	/* S509 - MUX_AUD_INT1# */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_OUT_HIGH,	/* S535 - LTE_DISABLE_L */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_INPUT,	/* S537 - RAM_ID0 */
+	GPIO_INPUT,	/* S538 - RAM_ID1 */
+	GPIO_INPUT,	/* S539 - RAM_ID2 */
+	GPIO_NC,	/* S540 - NC */
+	GPIO_NC,	/* S541 - NC */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+	[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/dptf.asl
new file mode 100644
index 000000000000..3530d7bc6da4
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/dptf.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	90
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	48
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	60
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	70
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 },	/* 0.128A */
+})
diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/mainboard.asl
new file mode 100644
index 000000000000..3cdd5c0cb21d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/mainboard.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Elan trackpad */
+#include <mainboard/google/rambi/acpi/trackpad_elan.asl>
diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h b/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h
new file mode 100644
index 000000000000..b4a6c6e4f5f7
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/orco/include/variant/onboard.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_IRQ              GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO        ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS          0
+#define BOARD_TRACKPAD_I2C_ADDR         0x15
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/variant.h b/src/mainboard/google/rambi/variants/orco/include/variant/variant.h
new file mode 100644
index 000000000000..ab8116222a21
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/orco/include/variant/variant.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+ * 0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
+ * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b111 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ */
+
+static const uint32_t dual_channel_config =
+	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/quawks/Makefile.inc b/src/mainboard/google/rambi/variants/quawks/Makefile.inc
new file mode 100644
index 000000000000..48956a111015
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/quawks/Makefile.inc
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+# 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b010 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+# 0b011 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBR 1600MHz
+# 0b100 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+# 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b110 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBR 1600MHz
+# 0b111 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+SPD_SOURCES = elpida_2GiB_dimm_EDJ4216EFBG-GNL-F
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/rambi/variants/quawks/devicetree.cb b/src/mainboard/google/rambi/variants/quawks/devicetree.cb
new file mode 100644
index 000000000000..cc5146d2e0a4
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/quawks/devicetree.cb
@@ -0,0 +1,98 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Quawks board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 on  end # I2C5
+		device pci 18.6 off end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 on  end # PCIE_PORT2
+		device pci 1c.2 off end # PCIE_PORT3
+		device pci 1c.3 off end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/rambi/variants/quawks/gpio.c b/src/mainboard/google/rambi/variants/quawks/gpio.c
new file mode 100644
index 000000000000..3d79d374412d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/quawks/gpio.c
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <mainboard/google/rambi/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_INPUT,	/* S0_NC07 - DDI1_DDCDATA - STRAP */
+	GPIO_NC,	/* S0_NC08 - NC */
+	GPIO_OUT_HIGH,	/* S0_NC09 - SOC_DISP_ON_C */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_FUNC2,	/* S0_SC001 - SATA_DEVSLP_C */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_FUNC1,	/* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+	GPIO_FUNC1,	/* S0-SC004 - PCIE_CLKREQ_WLAN# */
+	GPIO_NC,	/* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+	GPIO_NC,	/* S0-SC006 - PCIE_CLKREQ3# (NC) */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_FUNC(1, PULL_DOWN, 20K),	/* S0-SC033 - SD3_CLK */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC034 - SD3_D0 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC035 - SD3_D1 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC036 - SD3_D2 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_NC,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_NC,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_DIRQ,	/* S0-SC055 - TRACKPAD_INT_DX */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_INPUT,	/* S0-SC058 - SIM_DET_C */
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_DIRQ,	/* S0-SC070 - ALS_INT_L - INT */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_DIRQ,	/* S0-SC072 - TOUCH_INT_L_DX */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_INPUT,	/* S0-SC076 - BIOS_STRAP - STRAP */
+	GPIO_INPUT,	/* S0-SC077 - SOC_OVERRIDE - STRAP */
+	GPIO_FUNC1,	/* S0-SC078 - I2C_0_SDA */
+	GPIO_FUNC1,	/* S0-SC079 - I2C_0_SCL */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_FUNC1,	/* S0-SC086 - I2C_4_SDA */
+	GPIO_FUNC1,	/* S0-SC087 - I2C_4_SCL */
+	GPIO_FUNC1,	/* S0-SC088 - I2C_5_SDA */
+	GPIO_FUNC1,	/* S0-SC089 - I2C_5_SCL */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_WAKE,	/* S500 - PCH_WAKE# */
+	GPIO_ACPI_WAKE,	/* S501 - TRACKPAD_INT# - INT */
+	GPIO_ACPI_WAKE,	/* S502 - TOUCH_INT# - INT */
+	GPIO_FUNC6,	/* S503 - LTE_WAKE_L# - INT */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_FUNC1,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_NC,	/* S508 - NC */
+	GPIO_DIRQ,	/* S509 - MUX_AUD_INT1# */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_OUT_HIGH,	/* S535 - LTE_DISABLE_L */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_INPUT,	/* S537 - RAM_ID0 */
+	GPIO_INPUT,	/* S538 - RAM_ID1 */
+	GPIO_INPUT,	/* S539 - RAM_ID2 */
+	GPIO_NC,	/* S540 - NC */
+	GPIO_NC,	/* S541 - NC */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+	[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+	[ALS_IRQ_OFFSET] = ALS_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/dptf.asl
new file mode 100644
index 000000000000..7e3694666505
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/dptf.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	90
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	52
+#define DPTF_TSR0_CRITICAL	75
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	51
+#define DPTF_TSR1_CRITICAL	75
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	51
+#define DPTF_TSR2_CRITICAL	75
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6A4, "mA", 0 }, /* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x320, "mA", 0 },  /* 0.8A */
+	Package () { 0, 0, 0, 0, 16, 0x258, "mA", 0 },  /* 0.6A */
+	Package () { 0, 0, 0, 0, 8, 0x190, "mA", 0 },   /* 0.4A */
+	Package () { 0, 0, 0, 0, 0, 0x64, "mA", 0 },   /* 0.1A */
+})
diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/mainboard.asl
new file mode 100644
index 000000000000..3cdd5c0cb21d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/mainboard.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Elan trackpad */
+#include <mainboard/google/rambi/acpi/trackpad_elan.asl>
diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h b/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h
new file mode 100644
index 000000000000..4bb37be51c8c
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/quawks/include/variant/onboard.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_IRQ              GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO        ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS          0
+#define BOARD_TRACKPAD_I2C_ADDR         0x15
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+#define BOARD_ALS_IRQ                   GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h b/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h
new file mode 100644
index 000000000000..2b80bf460275
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+ * 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBR 1600MHz
+ * 0b011 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBR 1600MHz
+ * 0b100 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+ * 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b110 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBR 1600MHz
+ * 0b111 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBR 1600MHz
+ */
+
+static const uint32_t dual_channel_config =
+	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl
index acacc5fbbc91..f4bc3251cbde 100644
--- a/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/mainboard.asl
@@ -17,8 +17,8 @@
 /* Elan trackpad */
 #include <mainboard/google/rambi/acpi/trackpad_elan.asl>
 
-/* Amtel trackpad */
-#include <mainboard/google/rambi/acpi/trackpad_amtel.asl>
+/* Atmel trackpad */
+#include <mainboard/google/rambi/acpi/trackpad_atmel.asl>
 
-/* Amtel touchscreen trackpad */
-#include <mainboard/google/rambi/acpi/touchscreen_amtel.asl>
+/* Atmel touchscreen trackpad */
+#include <mainboard/google/rambi/acpi/touchscreen_atmel.asl>
diff --git a/src/mainboard/google/rambi/variants/squawks/Makefile.inc b/src/mainboard/google/rambi/variants/squawks/Makefile.inc
new file mode 100644
index 000000000000..48956a111015
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/squawks/Makefile.inc
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+# 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b010 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+# 0b011 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBR 1600MHz
+# 0b100 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+# 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b110 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBR 1600MHz
+# 0b111 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+SPD_SOURCES = elpida_2GiB_dimm_EDJ4216EFBG-GNL-F
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/rambi/variants/squawks/devicetree.cb b/src/mainboard/google/rambi/variants/squawks/devicetree.cb
new file mode 100644
index 000000000000..400a5513180f
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/squawks/devicetree.cb
@@ -0,0 +1,98 @@
+chip soc/intel/baytrail
+
+ 	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Squawks board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 on  end # I2C5
+		device pci 18.6 off end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 on  end # PCIE_PORT2
+		device pci 1c.2 off end # PCIE_PORT3
+		device pci 1c.3 off end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/rambi/variants/squawks/gpio.c b/src/mainboard/google/rambi/variants/squawks/gpio.c
new file mode 100644
index 000000000000..3d79d374412d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/squawks/gpio.c
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <mainboard/google/rambi/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_INPUT,	/* S0_NC07 - DDI1_DDCDATA - STRAP */
+	GPIO_NC,	/* S0_NC08 - NC */
+	GPIO_OUT_HIGH,	/* S0_NC09 - SOC_DISP_ON_C */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_FUNC2,	/* S0_SC001 - SATA_DEVSLP_C */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_FUNC1,	/* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+	GPIO_FUNC1,	/* S0-SC004 - PCIE_CLKREQ_WLAN# */
+	GPIO_NC,	/* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+	GPIO_NC,	/* S0-SC006 - PCIE_CLKREQ3# (NC) */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_FUNC(1, PULL_DOWN, 20K),	/* S0-SC033 - SD3_CLK */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC034 - SD3_D0 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC035 - SD3_D1 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC036 - SD3_D2 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_NC,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_NC,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_DIRQ,	/* S0-SC055 - TRACKPAD_INT_DX */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_INPUT,	/* S0-SC058 - SIM_DET_C */
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_DIRQ,	/* S0-SC070 - ALS_INT_L - INT */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_DIRQ,	/* S0-SC072 - TOUCH_INT_L_DX */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_INPUT,	/* S0-SC076 - BIOS_STRAP - STRAP */
+	GPIO_INPUT,	/* S0-SC077 - SOC_OVERRIDE - STRAP */
+	GPIO_FUNC1,	/* S0-SC078 - I2C_0_SDA */
+	GPIO_FUNC1,	/* S0-SC079 - I2C_0_SCL */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_FUNC1,	/* S0-SC086 - I2C_4_SDA */
+	GPIO_FUNC1,	/* S0-SC087 - I2C_4_SCL */
+	GPIO_FUNC1,	/* S0-SC088 - I2C_5_SDA */
+	GPIO_FUNC1,	/* S0-SC089 - I2C_5_SCL */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_WAKE,	/* S500 - PCH_WAKE# */
+	GPIO_ACPI_WAKE,	/* S501 - TRACKPAD_INT# - INT */
+	GPIO_ACPI_WAKE,	/* S502 - TOUCH_INT# - INT */
+	GPIO_FUNC6,	/* S503 - LTE_WAKE_L# - INT */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_FUNC1,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_NC,	/* S508 - NC */
+	GPIO_DIRQ,	/* S509 - MUX_AUD_INT1# */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_OUT_HIGH,	/* S535 - LTE_DISABLE_L */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_INPUT,	/* S537 - RAM_ID0 */
+	GPIO_INPUT,	/* S538 - RAM_ID1 */
+	GPIO_INPUT,	/* S539 - RAM_ID2 */
+	GPIO_NC,	/* S540 - NC */
+	GPIO_NC,	/* S541 - NC */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+	[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+	[ALS_IRQ_OFFSET] = ALS_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/dptf.asl
new file mode 100644
index 000000000000..b17f980c8da9
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/dptf.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	90
+#define DPTF_CPU_CRITICAL	100
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	53
+#define DPTF_TSR0_CRITICAL	80
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	80
+#define DPTF_TSR1_CRITICAL	90
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	53
+#define DPTF_TSR2_CRITICAL	100
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x7d0, "mA", 0 }, /* 2.0A */
+	Package () { 0, 0, 0, 0, 24, 0x6a4, "mA", 0 },  /* 1.7A */
+	Package () { 0, 0, 0, 0, 16, 0x578, "mA", 0 },  /* 1.4A */
+	Package () { 0, 0, 0, 0, 8, 0x3e8, "mA", 0 },   /* 1.0A */
+	Package () { 0, 0, 0, 0, 0, 0x258, "mA", 0 },   /* 0.6A */
+})
diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/mainboard.asl
new file mode 100644
index 000000000000..3cdd5c0cb21d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/mainboard.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Elan trackpad */
+#include <mainboard/google/rambi/acpi/trackpad_elan.asl>
diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h b/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h
new file mode 100644
index 000000000000..4bb37be51c8c
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/squawks/include/variant/onboard.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_IRQ              GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO        ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS          0
+#define BOARD_TRACKPAD_I2C_ADDR         0x15
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+#define BOARD_ALS_IRQ                   GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h b/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h
new file mode 100644
index 000000000000..2b80bf460275
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+ * 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBR 1600MHz
+ * 0b011 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBR 1600MHz
+ * 0b100 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+ * 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b110 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBR 1600MHz
+ * 0b111 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBR 1600MHz
+ */
+
+static const uint32_t dual_channel_config =
+	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/sumo/Makefile.inc b/src/mainboard/google/rambi/variants/sumo/Makefile.inc
new file mode 100644
index 000000000000..b2552d32b41e
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/sumo/Makefile.inc
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+# 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+# 0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
+# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+# 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b110 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+# 0b111 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125
+SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA
+SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/rambi/variants/sumo/devicetree.cb b/src/mainboard/google/rambi/variants/sumo/devicetree.cb
new file mode 100644
index 000000000000..89e2f2b0733c
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/sumo/devicetree.cb
@@ -0,0 +1,102 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Sumo board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+	register "usb2_comp_bg" = "0x4700"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 off end # I2C5
+		device pci 18.6 on  end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 off end # PCIE_PORT2
+		device pci 1c.2 on  end # PCIE_PORT3
+		device pci 1c.3 on  end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/rambi/variants/sumo/gpio.c b/src/mainboard/google/rambi/variants/sumo/gpio.c
new file mode 100644
index 000000000000..0856c29d2433
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/sumo/gpio.c
@@ -0,0 +1,228 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <mainboard/google/rambi/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_FUNC2,	/* S0_NC07 - DDI1_DDCDATA */
+	GPIO_FUNC2,	/* S0_NC08 - DDI1_DDCCLK */
+	GPIO_NC,	/* S0_NC09 - NC */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_NC,	/* S0_SC001 - NC */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_FUNC1,	/* S0-SC003 - PCIE_CLKREQ_IMAGE0# */
+	GPIO_NC,	/* S0-SC004 - NC# */
+	GPIO_FUNC1,	/* S0-SC005 - PCIE_CLKREQ_WLAN# */
+	GPIO_FUNC1,	/* S0-SC006 - PCIE_CLKREQ_LAN# */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_FUNC(1, PULL_DOWN, 20K),	/* S0-SC033 - SD3_CLK */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC034 - SD3_D0 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC035 - SD3_D1 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC036 - SD3_D2 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_FUNC1,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_FUNC1,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_NC,	/* S0-SC055 - NC */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_INPUT,	/* S0-SC058 - SIM_DET_C */
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_NC,	/* S0-SC070 - NC */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_DIRQ,	/* S0-SC072 - TOUCH_INT_L_DX */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_NC,	/* S0-SC076 - NC */
+	GPIO_NC,	/* S0-SC077 - NC */
+	GPIO_NC,	/* S0-SC078 - NC */
+	GPIO_NC,	/* S0-SC079 - NC */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_NC,	/* S0-SC086 - NC */
+	GPIO_NC,	/* S0-SC087 - NC */
+	GPIO_FUNC1,	/* S0-SC088 - I2C_5_SDA */
+	GPIO_FUNC1,	/* S0-SC089 - I2C_5_SCL */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_WAKE,	/* S500 - PCH_WAKE# */
+	GPIO_NC,	/* S501 - NC */
+	GPIO_ACPI_WAKE,	/* S502 - TOUCH_INT# - INT */
+	GPIO_FUNC6,	/* S503 - LTE_WAKE_L# - INT */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_FUNC1,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_INPUT,	/* S508 - SOC_RECOVER- */
+	GPIO_DIRQ,	/* S509 - MUX_AUD_INT1# */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_OUT_HIGH,	/* S535 - LTE_DISABLE_L */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_INPUT,	/* S537 - RAM_ID0 */
+	GPIO_INPUT,	/* S538 - RAM_ID1 */
+	GPIO_INPUT,	/* S539 - RAM_ID2 */
+	GPIO_NC,	/* S540 - NC */
+	GPIO_NC,	/* S541 - NC */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/dptf.asl
new file mode 100644
index 000000000000..3530d7bc6da4
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/dptf.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	90
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	48
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	60
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	70
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 },	/* 0.128A */
+})
diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/mainboard.asl
new file mode 100644
index 000000000000..e7f06ee2b791
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/mainboard.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* WDT touchscreen */
+#include <mainboard/google/rambi/acpi/touchscreen_wdt.asl>
diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h b/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h
new file mode 100644
index 000000000000..1fb268aa9b12
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/sumo/include/variant/onboard.h
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+#ifndef __ACPI__
+void lan_init(void);
+#endif
+
+/* defines for programming the MAC address */
+#define SUMO_NIC_VENDOR_ID		0x10EC
+#define SUMO_NIC_DEVICE_ID		0x8168
+
+/* 0x00: White LINK LED and Amber ACTIVE LED */
+#define SUMO_NIC_LED_MODE		0x00
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TOUCHSCREEN_NAME          "touchscreen"
+#define BOARD_TOUCHSCREEN_IRQ           GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET)
+#define BOARD_TOUCHSCREEN_WAKE_GPIO     ACPI_ENABLE_WAKE_SUS_GPIO(2)
+#define BOARD_TOUCHSCREEN_I2C_BUS       5
+#define BOARD_TOUCHSCREEN_I2C_ADDR      0x2c
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+
+/* Disable PS2 keyboard */
+#undef SIO_EC_ENABLE_PS2K
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h b/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h
new file mode 100644
index 000000000000..8d2113c06390
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+ * 0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
+ * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b101 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b110 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+ * 0b111 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63CFR-PBA 1600MHz
+ */
+
+static const uint32_t dual_channel_config =
+	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c
new file mode 100644
index 000000000000..07fe3d96b04f
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/sumo/lan.c
@@ -0,0 +1,191 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <string.h>
+#include <types.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <fmap.h>
+#include <variant/onboard.h>
+
+static unsigned int search(char *p, u8 *a, unsigned int lengthp,
+			   unsigned int lengtha)
+{
+	int i, j;
+
+	/* Searching */
+	for (j = 0; j <= lengtha - lengthp; j++) {
+		for (i = 0; i < lengthp && p[i] == a[i + j]; i++)
+			;
+		if (i >= lengthp)
+			return j;
+	}
+	return lengtha;
+}
+
+static unsigned char get_hex_digit(u8 *offset)
+{
+	unsigned char retval = 0;
+
+	retval = *offset - '0';
+	if (retval > 0x09) {
+		retval = *offset - 'A' + 0x0A;
+		if (retval > 0x0F)
+			retval = *offset - 'a' + 0x0a;
+	}
+	if (retval > 0x0F) {
+		printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n",
+			*offset, *offset);
+		retval = 0;
+	}
+
+	return retval;
+}
+
+static int get_mac_address(u32 *high_dword, u32 *low_dword,
+			   u8 *search_address, u32 search_length)
+{
+	char key[] = "ethernet_mac";
+	unsigned int offset;
+	int i;
+
+	offset = search(key, search_address, sizeof(key) - 1, search_length);
+	if (offset == search_length) {
+		printk(BIOS_DEBUG,
+		       "Error: Could not locate '%s' in VPD\n", key);
+		return 0;
+	}
+	printk(BIOS_DEBUG, "Located '%s' in VPD\n", key);
+
+	offset += sizeof(key);	/* move to next character */
+	*high_dword = 0;
+
+	/* Fetch the MAC address and put the octets in the correct order to
+	 * be programmed.
+	 *
+	 * From RTL8105E_Series_EEPROM-Less_App_Note_1.1
+	 * If the MAC address is 001122334455h:
+	 * Write 33221100h to I/O register offset 0x00 via double word access
+	 * Write 00005544h to I/O register offset 0x04 via double word access
+	 */
+
+	for (i = 0; i < 4; i++) {
+		*high_dword |= (get_hex_digit(search_address + offset)
+				<< (4 + (i * 8)));
+		*high_dword |= (get_hex_digit(search_address + offset + 1)
+				<< (i * 8));
+		offset += 3;
+	}
+
+	*low_dword = 0;
+	for (i = 0; i < 2; i++) {
+		*low_dword |= (get_hex_digit(search_address + offset)
+			       << (4 + (i * 8)));
+		*low_dword |= (get_hex_digit(search_address + offset + 1)
+			       << (i * 8));
+		offset += 3;
+	}
+
+	return *high_dword | *low_dword;
+}
+
+static void program_mac_address(u16 io_base)
+{
+	void *search_address = NULL;
+	size_t search_length = -1;
+
+	/* Default MAC Address of A0:00:BA:D0:0B:AD */
+	u32 high_dword = 0xD0BA00A0;	/* high dword of mac address */
+	u32 low_dword = 0x0000AD0B;	/* low word of mac address as a dword */
+
+	if (IS_ENABLED(CONFIG_CHROMEOS)) {
+		struct region_device rdev;
+
+		if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
+			search_address = rdev_mmap_full(&rdev);
+
+			if (search_address != NULL)
+				search_length = region_device_sz(&rdev);
+		}
+	} else {
+		search_address = cbfs_boot_map_with_leak("vpd.bin",
+							CBFS_TYPE_RAW,
+							&search_length);
+	}
+
+	if (search_address == NULL)
+		printk(BIOS_ERR, "LAN: VPD not found.\n");
+	else
+		get_mac_address(&high_dword, &low_dword, search_address,
+				search_length);
+
+	if (io_base) {
+		printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base);
+		printk(BIOS_DEBUG, "Programming MAC Address\n");
+
+		/* Disable register protection */
+		outb(0xc0, io_base + 0x50);
+		outl(high_dword, io_base);
+		outl(low_dword, io_base + 0x04);
+		outb(0x60, io_base + 54);
+		/* Enable register protection again */
+		outb(0x00, io_base + 0x50);
+	}
+}
+
+void lan_init(void)
+{
+	u16 io_base = 0;
+	struct device *ethernet_dev = NULL;
+
+	/* Get NIC's IO base address */
+	ethernet_dev = dev_find_device(SUMO_NIC_VENDOR_ID,
+				       SUMO_NIC_DEVICE_ID, 0);
+	if (ethernet_dev != NULL) {
+		io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe;
+
+		/*
+		 * Battery life time - LAN PCIe should enter ASPM L1 to save
+		 * power when LAN connection is idle.
+		 * enable CLKREQ: LAN pci config space 0x81h=01
+		 */
+		pci_write_config8(ethernet_dev, 0x81, 0x01);
+	}
+
+	if (io_base) {
+		/* Program MAC address based on VPD data */
+		program_mac_address(io_base);
+
+		/*
+		 * Program NIC LEDS
+		 *
+		 * RTL8105E Series EEPROM-Less Application Note,
+		 * Section 5.6 LED Mode Configuration
+		 *
+		 * Step1: Write C0h to I/O register 0x50 via byte access to
+		 *        disable 'register protection'
+		 * Step2: Write xx001111b to I/O register 0x52 via byte access
+		 *        (bit7 is LEDS1 and bit6 is LEDS0)
+		 * Step3: Write 0x00 to I/O register 0x50 via byte access to
+		 *        enable 'register protection'
+		 */
+		outb(0xc0, io_base + 0x50);	/* Disable protection */
+		outb((SUMO_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52);
+		outb(0x00, io_base + 0x50);	/* Enable register protection */
+	}
+}
diff --git a/src/mainboard/google/rambi/variants/swanky/Makefile.inc b/src/mainboard/google/rambi/variants/swanky/Makefile.inc
new file mode 100644
index 000000000000..1458ebb3850d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/swanky/Makefile.inc
@@ -0,0 +1,41 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b001 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+# 0b010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b011 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+SPD_SOURCES  = samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/rambi/variants/swanky/devicetree.cb b/src/mainboard/google/rambi/variants/swanky/devicetree.cb
new file mode 100644
index 000000000000..5e78a1025f4f
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/swanky/devicetree.cb
@@ -0,0 +1,101 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Swanky board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 on  end # I2C5
+		device pci 18.6 on  end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 on  end # PCIE_PORT2
+		device pci 1c.2 off end # PCIE_PORT3
+		device pci 1c.3 off end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/rambi/variants/swanky/gpio.c b/src/mainboard/google/rambi/variants/swanky/gpio.c
new file mode 100644
index 000000000000..a713549cd90d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/swanky/gpio.c
@@ -0,0 +1,229 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <mainboard/google/rambi/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_INPUT,	/* S0_NC07 - DDI1_DDCDATA - STRAP */
+	GPIO_NC,	/* S0_NC08 - NC */
+	GPIO_OUT_HIGH,	/* S0_NC09 - SOC_DISP_ON_C */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_FUNC2,	/* S0_SC001 - SATA_DEVSLP_C */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_FUNC1,	/* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+	GPIO_FUNC1,	/* S0-SC004 - PCIE_CLKREQ_WLAN# */
+	GPIO_NC,	/* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+	GPIO_NC,	/* S0-SC006 - PCIE_CLKREQ3# (NC) */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_FUNC(1, PULL_DOWN, 20K),	/* S0-SC033 - SD3_CLK */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC034 - SD3_D0 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC035 - SD3_D1 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC036 - SD3_D2 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_NC,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_NC,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_DIRQ,	/* S0-SC055 - TRACKPAD_INT_DX */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_INPUT,	/* S0-SC058 - SIM_DET_C */
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_NC,	/* S0-SC070 - ALS_INT_L - INT(NC) */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_DIRQ,	/* S0-SC072 - TOUCH_INT_L_DX */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_INPUT,	/* S0-SC076 - BIOS_STRAP - STRAP */
+	GPIO_INPUT,	/* S0-SC077 - SOC_OVERRIDE - STRAP */
+	GPIO_FUNC1,	/* S0-SC078 - I2C_0_SDA */
+	GPIO_FUNC1,	/* S0-SC079 - I2C_0_SCL */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_FUNC1,	/* S0-SC086 - I2C_4_SDA */
+	GPIO_FUNC1,	/* S0-SC087 - I2C_4_SCL */
+	GPIO_FUNC1,	/* S0-SC088 - I2C_5_SDA */
+	GPIO_FUNC1,	/* S0-SC089 - I2C_5_SCL */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_WAKE,	/* S500 - PCH_WAKE# */
+	GPIO_ACPI_WAKE,	/* S501 - TRACKPAD_INT# - INT */
+	GPIO_ACPI_WAKE,	/* S502 - TOUCH_INT# - INT */
+	GPIO_FUNC6,	/* S503 - LTE_WAKE_L# - INT */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_FUNC1,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_NC,	/* S508 - NC */
+	GPIO_DIRQ,	/* S509 - MUX_AUD_INT1# */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_OUT_HIGH,	/* S535 - LTE_DISABLE_L */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_INPUT,	/* S537 - RAM_ID0 */
+	GPIO_INPUT,	/* S538 - RAM_ID1 */
+	GPIO_INPUT,	/* S539 - RAM_ID2 */
+	GPIO_NC,	/* S540 - NC */
+	GPIO_INPUT,	/* S541 - PANEL_ID */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+	[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/dptf.asl
new file mode 100644
index 000000000000..e9b78a864f52
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/dptf.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	90
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	48
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	60
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	70
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 },	/* 0.128A */
+})
diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/mainboard.asl
new file mode 100644
index 000000000000..3cdd5c0cb21d
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/mainboard.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Elan trackpad */
+#include <mainboard/google/rambi/acpi/trackpad_elan.asl>
diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h b/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h
new file mode 100644
index 000000000000..f4ffed5e6121
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/swanky/include/variant/onboard.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_IRQ              GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO        ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS          0
+#define BOARD_TRACKPAD_I2C_ADDR         0x15
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h b/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h
new file mode 100644
index 000000000000..483983bc347e
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b001 - 2GiB total - 1 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b011 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
+ */
+
+static const uint32_t dual_channel_config =
+	(1 << 2) | (1 << 3);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/winky/Makefile.inc b/src/mainboard/google/rambi/variants/winky/Makefile.inc
new file mode 100644
index 000000000000..962f30c97b29
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/winky/Makefile.inc
@@ -0,0 +1,45 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 4GiB total - 2 x 2GB - micron HTTC4G63CFR-PBA_x16_4Gb
+# 0b001 - 4GiB total - 2 x Samsung_2Gib_K4B4G1646Q-HYK0
+# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+# 0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
+# 0b100 - 2GiB total - 1 x 2GB - micron HTTC4G63CFR-PBA_x16_4Gb
+# 0b101 - 2GiB total - 1 x Samsung_2Gib_K4B4G1646Q-HYK0
+SPD_SOURCES =  HT_micron_HTTC4G63CFR-PBA_x16_4Gb
+SPD_SOURCES += Samsung_2Gib_K4B4G1646Q-HYK0
+SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125
+SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA
+SPD_SOURCES += HT_micron_HTTC4G63CFR-PBA_x16_4Gb
+SPD_SOURCES += Samsung_2Gib_K4B4G1646Q-HYK0
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/rambi/variants/winky/devicetree.cb b/src/mainboard/google/rambi/variants/winky/devicetree.cb
new file mode 100644
index 000000000000..6d52b89e4822
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/winky/devicetree.cb
@@ -0,0 +1,102 @@
+chip soc/intel/baytrail
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x1"
+	register "sata_ahci" = "0x1"
+	register "ide_legacy_combined" = "0x0"
+
+	# Route USB ports to XHCI
+	register "usb_route_to_xhci" = "1"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Winky board
+	register "usb2_comp_bg"        = "0x4680"
+	register "usb2_per_port_lane0" = "0x0004C209"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x0004B209"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# LPE audio codec settings
+	register "lpe_codec_clk_freq" = "25" # 25MHz clock
+	register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
+
+	# SD Card controller
+	register "sdcard_cap_low" = "0x036864b2"
+	register "sdcard_cap_high" = "0x0"
+
+	# Enable devices in ACPI mode
+	register "lpe_acpi_mode" = "1"
+	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# Enable PIPEA as DP_C
+	register "gpu_pipea_port_select" = "2"		# DP_C
+	register "gpu_pipea_power_cycle_delay" = "6"	# 600ms
+	register "gpu_pipea_power_on_delay" = "5000"	# 500ms
+	register "gpu_pipea_light_on_delay" = "70"	# 7ms
+	register "gpu_pipea_power_off_delay" = "500"	# 50ms
+	register "gpu_pipea_light_off_delay" = "2000"	# 200ms
+
+	# VR PS2 control
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 11.0 off end # SDIO
+		device pci 12.0 on  end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 on  end # LPE
+		device pci 17.0 on  end # MMC
+		device pci 18.0 on  end # SIO_DMA1
+		device pci 18.1 on  end # I2C1
+		device pci 18.2 on  end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 off end # I2C5
+		device pci 18.6 off end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA
+		device pci 1c.0 on  end # PCIE_PORT1
+		device pci 1c.1 on  end # PCIE_PORT2
+		device pci 1c.2 off end # PCIE_PORT3
+		device pci 1c.3 off end # PCIE_PORT4
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 on  end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
+		device pci 1f.3 off end # SMBus
+	end
+end
diff --git a/src/mainboard/google/rambi/variants/winky/gpio.c b/src/mainboard/google/rambi/variants/winky/gpio.c
new file mode 100644
index 000000000000..dcdf6f5d7672
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/winky/gpio.c
@@ -0,0 +1,228 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <mainboard/google/rambi/irqroute.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,	/* S0_NC00 - INT_HDMI_HPD - INT */
+	GPIO_FUNC2,	/* S0_NC01 - HDMI_DDCDATA_SW */
+	GPIO_FUNC2,	/* S0_NC02 - HDMI_DDCCLK_SW */
+	GPIO_NC,	/* S0_NC03 - NC */
+	GPIO_NC,	/* S0_NC04 - NC */
+	GPIO_NC,	/* S0_NC05 - NC */
+	GPIO_FUNC2,	/* S0_NC06 - EDP_HPD_L */
+	GPIO_INPUT,	/* S0_NC07 - DDI1_DDCDATA - STRAP */
+	GPIO_NC,	/* S0_NC08 - NC */
+	GPIO_OUT_HIGH,	/* S0_NC09 - SOC_DISP_ON_C */
+	GPIO_FUNC2,	/* S0_NC10 - SOC_EDP_BLON_C */
+	GPIO_FUNC2,	/* S0_NC11 - SOC_DPST_PWM_C */
+	GPIO_NC,	/* S0_NC12 - NC */
+	GPIO_INPUT,	/* S0_NC13 - GPIO_NC13 - STRAP */
+	GPIO_NC,	/* S0_NC14 - NC */
+	GPIO_DEFAULT,	/* S0_NC15 - XDP_GPIO_S0_NC15 */
+	GPIO_DEFAULT,	/* S0_NC16 - XDP_GPIO_S0_NC16 */
+	GPIO_DEFAULT,	/* S0_NC17 - XDP_GPIO_S0_NC17 */
+	GPIO_DEFAULT,	/* S0_NC18 - XDP_GPIO_S0_NC18 */
+	GPIO_DEFAULT,	/* S0_NC19 - XDP_GPIO_S0_NC19 */
+	GPIO_DEFAULT,	/* S0_NC20 - XDP_GPIO_S0_NC20 */
+	GPIO_DEFAULT,	/* S0_NC21 - XDP_GPIO_S0_NC21 */
+	GPIO_DEFAULT,	/* S0_NC22 - XDP_GPIO_S0_NC22 */
+	GPIO_DEFAULT,	/* S0_NC23 - XDP_GPIO_S0_NC23 */
+	GPIO_NC,	/* S0_NC24 - NC */
+	GPIO_NC,	/* S0_NC25 - NC */
+	GPIO_NC,	/* S0_NC26 - NC */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_ACPI_SCI,	/* S0_SC000 - SOC_KBC_SCI - INT */
+	GPIO_FUNC2,	/* S0_SC001 - SATA_DEVSLP_C */
+	GPIO_NC,	/* S0-SC002 - SATA_LED_R_N (NC/PU) */
+	GPIO_FUNC1,	/* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+	GPIO_FUNC1,	/* S0-SC004 - PCIE_CLKREQ_WLAN# */
+	GPIO_NC,	/* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+	GPIO_NC,	/* S0-SC006 - PCIE_CLKREQ3# (NC) */
+	GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+	GPIO_NC,	/* S0-SC008 - ACZ_RST# (NC) */
+	GPIO_NC,	/* S0-SC009 - ACZ_SYNC (NC) */
+	GPIO_NC,	/* S0-SC010 - ACZ_BCLK (NC) */
+	GPIO_NC,	/* S0-SC011 - ACZ_STDOUT (NC) */
+	GPIO_NC,	/* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+	GPIO_NC,	/* S0-SC013 - NC */
+	GPIO_INPUT,	/* S0-SC014 - DET_TRIGGER - INT */
+	GPIO_INPUT,	/* S0-SC015 - AJACK_MICPRES_L - INT */
+	GPIO_FUNC(3, PULL_DOWN, 20K),	/* S0-SC016 - MMC1_45_CLK  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC017 - MMC1_45_D[0] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC018 - MMC1_45_D[1] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC019 - MMC1_45_D[2] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC020 - MMC1_45_D[3] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC021 - MMC1_45_D[4] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC022 - MMC1_45_D[5] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC023 - MMC1_45_D[6] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC024 - MMC1_45_D[7] */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC025 - MMC1_45_CMD  */
+	GPIO_FUNC(3, PULL_UP, 20K),	/* S0-SC026 - MMC1_45_RST  */
+	GPIO_NC,	/* S0-SC027 - NC */
+	GPIO_NC,	/* S0-SC028 - NC */
+	GPIO_NC,	/* S0-SC029 - NC */
+	GPIO_NC,	/* S0-SC030 - NC */
+	GPIO_NC,	/* S0-SC031 - NC */
+	GPIO_NC,	/* S0-SC032 - NC */
+	GPIO_FUNC(1, PULL_DOWN, 20K),	/* S0-SC033 - SD3_CLK */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC034 - SD3_D0 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC035 - SD3_D1 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC036 - SD3_D2 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC037 - SD3_D3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC038 - SD3_CD# */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC039 - SD3_CMD */
+	GPIO_NC,	/* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+	GPIO_FUNC(1, PULL_UP, 20K),	/* S0-SC041 - SDIO3_PWR_EN# */
+	GPIO_FUNC1,	/* S0-SC042 - LPC_LAD0 */
+	GPIO_FUNC1,	/* S0-SC043 - LPC-LAD1 */
+	GPIO_FUNC1,	/* S0-SC044 - LPC_LAD2 */
+	GPIO_FUNC1,	/* S0-SC045 - LPC_LAD3 */
+	GPIO_FUNC1,	/* S0-SC046 - LPC_LFRAME# */
+	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
+	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
+	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
+	GPIO_NC,	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_NC,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
+	GPIO_NC,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
+	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
+	GPIO_DEFAULT,	/* S0-SC054 - NC */
+	GPIO_DIRQ,	/* S0-SC055 - TRACKPAD_INT_DX */
+	GPIO_INPUT,	/* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+	GPIO_FUNC1,	/* S0-SC057 - PCH_UART_TXD */
+	GPIO_INPUT,	/* S0-SC058 - SIM_DET_C */
+	GPIO_INPUT_LEGACY,	/* S0-SC059 - EC_IN_RW_C */
+	GPIO_NC,	/* S0-SC060 - NC */
+	GPIO_FUNC1,	/* S0-SC061 - SOC_UART_RX */
+	GPIO_FUNC1,	/* S0-SC062 - I2S_BCLK */
+	GPIO_FUNC1,	/* S0-SC063 - I2S_LRCLK */
+	GPIO_FUNC1,	/* S0-SC064 - I2S_DIN */
+	GPIO_FUNC1,	/* S0-SC065 - I2S_DOUT */
+	GPIO_FUNC1,	/* S0-SC066 - SIO_SPI_CS# */
+	GPIO_FUNC1,	/* S0-SC067 - SIO_SPI_MISO */
+	GPIO_FUNC1,	/* S0-SC068 - SIO_SPI_MOSI */
+	GPIO_FUNC1,	/* S0-SC069 - SIO_SPI_CLK */
+	GPIO_NC,	/* S0-SC070 - ALS_INT_L - INT */
+	GPIO_NC,	/* S0-SC071 - NC */
+	GPIO_NC,	/* S0-SC072 - TOUCH_INT_L_DX */
+	GPIO_NC,	/* S0-SC073 - NC */
+	GPIO_NC,	/* S0-SC074 - SIO_UART2_RXD (NC) */
+	GPIO_NC,	/* S0-SC075 - SIO_UART2_TXD (NC) */
+	GPIO_INPUT,	/* S0-SC076 - BIOS_STRAP - STRAP */
+	GPIO_INPUT,	/* S0-SC077 - SOC_OVERRIDE - STRAP */
+	GPIO_FUNC1,	/* S0-SC078 - I2C_0_SDA */
+	GPIO_FUNC1,	/* S0-SC079 - I2C_0_SCL */
+	GPIO_FUNC1,	/* S0-SC080 - I2C_1_SDA */
+	GPIO_FUNC1,	/* S0-SC081 - I2C_1_SCL */
+	GPIO_NC,	/* S0-SC082 - NC */
+	GPIO_NC,	/* S0-SC083 - NC */
+	GPIO_NC,	/* S0-SC084 - NC */
+	GPIO_NC,	/* S0-SC085 - NC */
+	GPIO_NC,	/* S0-SC086 - NC */
+	GPIO_NC,	/* S0-SC087 - NC */
+	GPIO_NC,	/* S0-SC088 - NC */
+	GPIO_NC,	/* S0-SC089 - NC */
+	GPIO_NC,	/* S0-SC090 - NC */
+	GPIO_NC,	/* S0-SC091 - NC */
+	GPIO_NC,	/* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+	GPIO_NC,	/* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+	GPIO_NC,	/* S0-SC094 - NC */
+	GPIO_NC,	/* S0-SC095 - SIO_PWM1 (NC) */
+	GPIO_FUNC1,	/* S0-SC096 - I2S_MCLK */
+	GPIO_NC,	/* S0-SC097 - NC */
+	GPIO_NC,	/* S0-SC098 - NC */
+	GPIO_NC,	/* S0-SC099 - NC */
+	GPIO_NC,	/* S0-SC100 - NC */
+	GPIO_DIRQ,	/* S0-SC101 - KBD_IRQ# */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_ACPI_WAKE,	/* S500 - PCH_WAKE# */
+	GPIO_ACPI_WAKE,	/* S501 - TRACKPAD_INT# - INT */
+	GPIO_NC,	/* S502 - TOUCH_INT# - INT */
+	GPIO_NC,	/* S503 - LTE_WAKE_L# - INT */
+	GPIO_NC,	/* S504 - SOC_JTAG2_TDO (NC/PU) */
+	GPIO_NC,	/* S505 - SUS_CLK_WLAN (NC) */
+	GPIO_INPUT_PU,	/* S506 - PCH_SPI_WP */
+	GPIO_ACPI_SMI,	/* S507 - SOC_KBC_SMI - INT */
+	GPIO_NC,	/* S508 - NC */
+	GPIO_DIRQ,	/* S509 - MUX_AUD_INT1# */
+	GPIO_OUT_HIGH,	/* S510 - WIFI_DISABLE_L */
+	GPIO_FUNC0,	/* S511 - SUSPWRDNACK */
+	GPIO_FUNC0,	/* S512 - WIFI_SUSCLK */
+	GPIO_FUNC0,	/* S513 - SLP_SX */
+	GPIO_NC,	/* S514 - NC */
+	GPIO_FUNC0,	/* S515 - WLAN_WAKE_L - INT */
+	GPIO_FUNC0,	/* S516 - PCH_PWRBTN_L */
+	GPIO_NC,	/* S517 - NC */
+	GPIO_FUNC0,	/* S518 - SUS_STAT# */
+	GPIO_FUNC0,	/* S519 - USB_OC0# */
+	GPIO_FUNC0,	/* S520 - USB_OC1# */
+	GPIO_NC,	/* S521 - NC */
+	GPIO_NC,	/* S522 - XDP_GPIO_DFX0 */
+	GPIO_NC,	/* S523 - XDP_GPIO_DFX1 */
+	GPIO_NC,	/* S524 - XDP_GPIO_DFX2 */
+	GPIO_NC,	/* S525 - XDP_GPIO_DFX3 */
+	GPIO_NC,	/* S526 - XDP_GPIO_DFX4 */
+	GPIO_NC,	/* S527 - XDP_GPIO_DFX5 */
+	GPIO_NC,	/* S528 - XDP_GPIO_DFX6 */
+	GPIO_NC,	/* S529 - XDP_GPIO_DFX7 */
+	GPIO_NC,	/* S530 - XDP_GPIO_DFX8 */
+	GPIO_NC,	/* S531 - NC */
+	GPIO_NC,	/* S532 - NC */
+	GPIO_NC,	/* S533 - NC */
+	GPIO_NC,	/* S534 - NC */
+	GPIO_OUT_HIGH,	/* S535 - LTE_DISABLE_L */
+	GPIO_NC,	/* S536 - NC */
+	GPIO_INPUT,	/* S537 - RAM_ID0 */
+	GPIO_INPUT,	/* S538 - RAM_ID1 */
+	GPIO_INPUT,	/* S539 - RAM_ID2 */
+	GPIO_NC,	/* S540 - NC */
+	GPIO_NC,	/* S541 - NC */
+	GPIO_NC,	/* S542 - NC */
+	GPIO_NC,	/* S543 - NC */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+	[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/acpi/dptf.asl b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/dptf.asl
new file mode 100644
index 000000000000..3530d7bc6da4
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/dptf.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE	80
+#define DPTF_CPU_CRITICAL	90
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
+#define DPTF_TSR0_PASSIVE	48
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE	60
+#define DPTF_TSR1_CRITICAL	70
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	70
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 },	/* 1.7A (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1.5A */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1.0A */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 0.5A */
+	Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 },	/* 0.128A */
+})
diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/acpi/mainboard.asl b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/mainboard.asl
new file mode 100644
index 000000000000..184ef83482fd
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/mainboard.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Atmel trackpad */
+#include <mainboard/google/rambi/acpi/trackpad_atmel.asl>
diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h b/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h
new file mode 100644
index 000000000000..977117953120
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/winky/include/variant/onboard.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include <mainboard/google/rambi/irqroute.h>
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO             ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME             "trackpad"
+#define BOARD_TRACKPAD_IRQ              GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO        ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS          0
+#define BOARD_TRACKPAD_I2C_ADDR         0x4b
+
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ                 GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+#define BOARD_ALS_IRQ                   GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/variant.h b/src/mainboard/google/rambi/variants/winky/include/variant/variant.h
new file mode 100644
index 000000000000..6bf556965f16
--- /dev/null
+++ b/src/mainboard/google/rambi/variants/winky/include/variant/variant.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_H
+#define VARIANT_H
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b001 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0
+ * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+ * 0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
+ * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b101 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0
+ */
+
+static const uint32_t dual_channel_config =
+	(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+#endif