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| author | Werner Zeh <werner.zeh@siemens.com> | 2021-11-03 11:44:43 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-04 11:05:03 +0000 |
| commit | 9f7e018f0f5875fce167a75325ee08969672411c (patch) | |
| tree | 623683ba9843abd600e63d5029ea7eb08c9c32c1 | |
| parent | 9916eb400f0c58d316d5592c5c8629676925601f (diff) | |
| download | coreboot-9f7e018f0f5875fce167a75325ee08969672411c.tar.gz coreboot-9f7e018f0f5875fce167a75325ee08969672411c.tar.bz2 coreboot-9f7e018f0f5875fce167a75325ee08969672411c.zip | |
mb/siemens/mc_ehl: Disable PMC low power modes
All the mainboard variants of mc_ehl do not use the external switches
for the bypass rails. Disable the matching UPDs and all the low power
modes of the PMC.
Change-Id: I08f4effe5c4d5845bed01dfe1bd1251c58012b7f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58895
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/mainboard.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c index fc03115a8e9a..5c8f5849dfe2 100644 --- a/src/mainboard/siemens/mc_ehl/mainboard.c +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -125,6 +125,11 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) /* Disable P-States */ params->MaxRatio = 0; + + /* Disable PMC low power modes */ + params->PmcLpmS0ixSubStateEnableMask = 0; + params->PmcV1p05PhyExtFetControlEn = 0; + params->PmcV1p05IsExtFetControlEn = 0; } static void mainboard_init(void *chip_info) |