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| author | Felix Singer <felixsinger@posteo.net> | 2021-12-31 00:30:55 +0100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2022-05-26 11:48:52 +0000 |
| commit | a182faeb88a0b2313ac83371fdefd6ca0d30bb8d (patch) | |
| tree | a15f645c98f39e7cbd98e90dfb6acb82882a8d74 | |
| parent | b9652482ce4556183c3b8f90de2c0a71b22d6691 (diff) | |
| download | coreboot-a182faeb88a0b2313ac83371fdefd6ca0d30bb8d.tar.gz coreboot-a182faeb88a0b2313ac83371fdefd6ca0d30bb8d.tar.bz2 coreboot-a182faeb88a0b2313ac83371fdefd6ca0d30bb8d.zip | |
soc/intel/alderlake: Hook up FSP hyper-threading setting to option API
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Change-Id: I520a936b4c3a8997ba2c6bea0126b3bbcc5d68ce
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 4 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 1507d6f235f1..4e10f3d2de3b 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -53,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select HAVE_DEBUG_RAM_SETUP select HAVE_FSP_GOP + select HAVE_HYPERTHREADING select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 863fc43ffafe..38d7c67bdc65 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -10,6 +10,7 @@ #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/pcie_rp.h> +#include <option.h> #include <soc/gpio_soc_defs.h> #include <soc/iomap.h> #include <soc/msr.h> @@ -158,8 +159,7 @@ static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; - /* Enable Hyper Threading */ - m_cfg->HyperThreading = 1; + m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING)); } static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, |