summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorNico Huber <nico.huber@secunet.com>2018-12-06 12:45:15 +0100
committerNico Huber <nico.h@gmx.de>2019-01-10 09:24:47 +0000
commitab4eb2afc34266b53c6201bbca907dcb2ff07410 (patch)
treec5d4d4a032c138f7c053124a88872b315695a591
parentf5ca922c879995a151f4ffefd52bfff34fee21ca (diff)
downloadcoreboot-ab4eb2afc34266b53c6201bbca907dcb2ff07410.tar.gz
coreboot-ab4eb2afc34266b53c6201bbca907dcb2ff07410.tar.bz2
coreboot-ab4eb2afc34266b53c6201bbca907dcb2ff07410.zip
3rdparty/blobs: Update for current Intel microcode
The microcode included for `model_6xx` was for a 660, that path has changed. Change-Id: I09a41a8269cfdf8953bac10c9630922192851e73 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
m---------3rdparty/blobs0
-rw-r--r--src/cpu/intel/model_6xx/Makefile.inc2
2 files changed, 1 insertions, 1 deletions
diff --git a/3rdparty/blobs b/3rdparty/blobs
-Subproject 5b9c768f37991591409f5db6ecfb02fdd0c6319
+Subproject 16058e552279b4884b1f671e7a78752d28abd1c
diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc
index 1ac799e45270..3ac510fa44d8 100644
--- a/src/cpu/intel/model_6xx/Makefile.inc
+++ b/src/cpu/intel/model_6xx/Makefile.inc
@@ -1,3 +1,3 @@
ramstage-y += model_6xx_init.c
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_66x/microcode.bin