diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2022-12-21 22:10:55 -0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-11-01 04:19:25 +0000 |
| commit | ab77ba7dfe5b40f86a20028a5c528613875096e5 (patch) | |
| tree | 053f5c7e321b745a3d91b7e4998fe1cf9f321f28 | |
| parent | 35348fc0058c514653228f8e53d30181cff794d1 (diff) | |
| download | coreboot-ab77ba7dfe5b40f86a20028a5c528613875096e5.tar.gz coreboot-ab77ba7dfe5b40f86a20028a5c528613875096e5.tar.bz2 coreboot-ab77ba7dfe5b40f86a20028a5c528613875096e5.zip | |
mb/google/rex/var/rex0: Toggle NVMe PWR pin to reset SSD
During warm reboot, NVMe is not detected with non-serial image
sometimes while there is no issue with serial image. This change
toggles NVMe PWR pin as soon as in early stage to make NVMe ready
sooner.
BUG=b:260547988
BRANCH=None
TEST= Build rex0 and try warm reboot from OS console. Check if
the platform with Micron SSD boots to OS again without an issue.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I2f34e3f49e7fc388198ff85c8e119cb3f242a60e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/gpio.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c index 6cd24b7803df..184c4d2b73db 100644 --- a/src/mainboard/google/rex/variants/rex0/gpio.c +++ b/src/mainboard/google/rex/variants/rex0/gpio.c @@ -376,6 +376,11 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A19, 0, DEEP), + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 1, DEEP), + /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), /* GPP_B17 : [] ==> EN_WWAN_PWR */ @@ -410,14 +415,14 @@ static const struct pad_config early_gpio_table[] = { /* GPP_E13 : [] ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* GPP_A20 : [] ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_A20, 0, DEEP), - /* GPP_H10 : [] ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), }; static const struct pad_config romstage_gpio_table[] = { + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A19, 1, DEEP), + /* GPP_B11 : [] ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* A20 : [] ==> SSD_PERST_L */ |