diff options
| author | Benjamin Doron <benjamin.doron00@gmail.com> | 2020-12-12 22:42:41 +0000 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-12-17 20:05:49 +0000 |
| commit | ac857ca3b166d385caa4faf62b4f1b8fc3b3f2da (patch) | |
| tree | 7dadb9454b084736d7a931b8cb98c5da5dfe11db | |
| parent | a04400d1aac35299568774304cf9664188570d07 (diff) | |
| download | coreboot-ac857ca3b166d385caa4faf62b4f1b8fc3b3f2da.tar.gz coreboot-ac857ca3b166d385caa4faf62b4f1b8fc3b3f2da.tar.bz2 coreboot-ac857ca3b166d385caa4faf62b4f1b8fc3b3f2da.zip | |
soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration
coreboot already unconditionally enables CLKRUN_EN in SoC common code.
Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN]
of LPC is still enabled.
Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/51nb/x210/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/kontron/bsl6/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 5 |
4 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 43f272e5a8cc..b51c73c48614 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -56,8 +56,6 @@ chip soc/intel/skylake register "serirq_mode" = "SERIRQ_CONTINUOUS" - register "PmConfigPciClockRun" = "1" - # Enable Root Ports 3, 4 and 9 register "PcieRpEnable[2]" = "1" # Ethernet controller register "PcieRpClkReqSupport[2]" = "1" diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index 6bdfcaf50143..8ad785251d8d 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -10,7 +10,6 @@ chip soc/intel/skylake register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" - register "PmConfigPciClockRun" = "1" register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S" # VR Settings Configuration for 2 Domains diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index c9519cdc29ac..ef16f388d793 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -338,7 +338,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; - params->PchPmLpcClockRun = config->PmConfigPciClockRun; params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; params->PchPmPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index f4744c96314f..7d9d93460c29 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -377,11 +377,6 @@ struct soc_intel_skylake_config { } PmConfigSlpAMinAssert; /* - * This member describes whether or not the PCI ClockRun feature of PCH - * should be enabled. Values 0: Disabled, 1: Enabled - */ - u8 PmConfigPciClockRun; - /* * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, * 1: Enabled */ |