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authorFelix Held <felix-coreboot@felixheld.de>2021-08-03 15:53:36 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-09-08 00:16:16 +0000
commitad38ac01823c9d2635b396e7dcb568076230935a (patch)
tree874de6b20a29e567eed4ae0c99c3fcd3f7fab743
parentafa750bf5788fefa58cbfb9783906cf547fc47a8 (diff)
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soc/amd/common/block/gpio_banks: move GPIO MUX access functions
Move those two functions near the top of the file to have all functions that do the hardware accesses in one place. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If787e6e1d124a932beafd73e5ce7d0ce4869e800 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
-rw-r--r--src/soc/amd/common/block/gpio_banks/gpio.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c
index 0f9711849747..6f566341eba3 100644
--- a/src/soc/amd/common/block/gpio_banks/gpio.c
+++ b/src/soc/amd/common/block/gpio_banks/gpio.c
@@ -31,6 +31,17 @@ static inline void gpio_write32(gpio_t gpio_num, uint32_t value)
write32(gpio_ctrl_ptr(gpio_num), value);
}
+static uint8_t get_gpio_mux(gpio_t gpio)
+{
+ return iomux_read8(gpio);
+}
+
+static void set_gpio_mux(gpio_t gpio, uint8_t function)
+{
+ iomux_write8(gpio, function & AMD_GPIO_MUX_MASK);
+ get_gpio_mux(gpio); /* Flush posted write */
+}
+
static int get_gpio_gevent(gpio_t gpio, const struct soc_amd_event *table,
size_t items)
{
@@ -176,17 +187,6 @@ uint16_t gpio_acpi_pin(gpio_t gpio)
return gpio;
}
-static uint8_t get_gpio_mux(gpio_t gpio)
-{
- return iomux_read8(gpio);
-}
-
-static void set_gpio_mux(gpio_t gpio, uint8_t function)
-{
- iomux_write8(gpio, function & AMD_GPIO_MUX_MASK);
- get_gpio_mux(gpio); /* Flush posted write */
-}
-
void gpio_save_pin_registers(gpio_t gpio, struct soc_amd_gpio_register_save *save)
{
save->mux_value = get_gpio_mux(gpio);