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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-05-21 09:04:16 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:12:19 +0000 |
| commit | ae22fe293fc97a9f6b0fbf52230277b2a4332cda (patch) | |
| tree | cae4d7cb79e527ba92b8a3ce1022c14693e77a4b | |
| parent | 2f2191a3d0876fb90ab0c5f09e1c802b0a89b83e (diff) | |
| download | coreboot-ae22fe293fc97a9f6b0fbf52230277b2a4332cda.tar.gz coreboot-ae22fe293fc97a9f6b0fbf52230277b2a4332cda.tar.bz2 coreboot-ae22fe293fc97a9f6b0fbf52230277b2a4332cda.zip | |
sb/intel/i82801gx: Use macro instead of numbers
Change-Id: Ide6516937ea79c35cd54127ed2823352a1cac6d4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41611
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/southbridge/intel/i82801gx/ac97.c | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_smbus.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/ide.c | 16 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/pcie.c | 2 |
4 files changed, 12 insertions, 11 deletions
diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c index 175b5cd657b1..67426c7323fa 100644 --- a/src/southbridge/intel/i82801gx/ac97.c +++ b/src/southbridge/intel/i82801gx/ac97.c @@ -4,6 +4,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_def.h> #include <arch/io.h> #include <device/pci_ops.h> #include <delay.h> @@ -96,7 +97,7 @@ static void init_cnr(void) static void program_sigid(struct device *dev, u32 id) { - pci_write_config32(dev, 0x2c, id); + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, id); } static void ac97_audio_init(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 7cd4a671d58e..4d4ecb18c523 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -16,7 +16,7 @@ int smbus_enable_iobar(uintptr_t base) const pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x2) != 0x27da) + if (pci_read_config16(dev, PCI_DEVICE_ID) != 0x27da) return -1; /* Set SMBus I/O base. */ diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index f1ccd0f295d4..5c4c96d8c878 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -40,10 +40,10 @@ static void ide_init(struct device *dev) if (enable_primary) { /* Enable primary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - ideTimingConfig |= (2 << 12); // ISP = 3 clocks - ideTimingConfig |= (3 << 8); // RCT = 1 clock - ideTimingConfig |= (1 << 1); // IE0 - ideTimingConfig |= (1 << 0); // TIME0 + ideTimingConfig |= IDE_ISP_3_CLOCKS; + ideTimingConfig |= IDE_RCT_1_CLOCKS; + ideTimingConfig |= IDE_IE0; + ideTimingConfig |= IDE_TIME0; // TIME0 printk(BIOS_DEBUG, " IDE0"); } pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); @@ -54,10 +54,10 @@ static void ide_init(struct device *dev) if (enable_secondary) { /* Enable secondary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - ideTimingConfig |= (2 << 12); // ISP = 3 clocks - ideTimingConfig |= (3 << 8); // RCT = 1 clock - ideTimingConfig |= (1 << 1); // IE0 - ideTimingConfig |= (1 << 0); // TIME0 + ideTimingConfig |= IDE_ISP_3_CLOCKS; + ideTimingConfig |= IDE_RCT_1_CLOCKS; + ideTimingConfig |= IDE_IE0; + ideTimingConfig |= IDE_TIME0; printk(BIOS_DEBUG, " IDE1"); } pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 56cf1f287db4..7a49e528596d 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -50,7 +50,7 @@ static void pci_init(struct device *dev) /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it - pci_write_config8(dev, 0x0c, 0x10); + pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 0x10); reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); reg16 &= ~PCI_BRIDGE_CTL_PARITY; |