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| author | Dinesh Gehlot <digehlot@google.com> | 2023-08-17 11:04:32 +0530 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-18 14:12:41 +0000 |
| commit | b60cf3d135c502334e8c9b4b940c53e86058f053 (patch) | |
| tree | 2ec5d8ac14398bd6e15f01d0e844d665552ff002 | |
| parent | 6a0c6d7124ae783cfc608f39e709190da4148b40 (diff) | |
| download | coreboot-b60cf3d135c502334e8c9b4b940c53e86058f053.tar.gz coreboot-b60cf3d135c502334e8c9b4b940c53e86058f053.tar.bz2 coreboot-b60cf3d135c502334e8c9b4b940c53e86058f053.zip | |
vc/intel/fsp/mtl: Update header files from 3223.80 to 3292.83
Update header files for FSP for Meteor Lake platform to version 3292.83,
previous version being 3223.80.
The patch doesn't include any function changes, only a few comments and
headers have been changed.
BUG=b:295126631
TEST=Able to build and boot google/rex to ChromeOS.
Change-Id: I27f88732bfafd4732ea39bf9c54e18341dd26cf9
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h | 8 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h | 2 |
2 files changed, 4 insertions, 6 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h index c0424c707678..52677b096c87 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h @@ -1445,16 +1445,14 @@ typedef struct { UINT16 IccLimit[6]; /** Offset 0x0766 - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled. - Enable/Disable VR FastVmode; [0] for IA, [1] for GT, 0: Disable; <b>1: Enable</b>. - [2] for SA, <b>0: Disable</b>; 1: Enable. + Enable/Disable VR FastVmode; 0: Disable; <b>1: Enable</b>. For all VR by domain 0: Disable, 1: Enable **/ UINT8 EnableFastVmode[6]; /** Offset 0x076C - Enable CEP - Enable/Disable CEP (Current Excursion Protection) Support. [0] for IA, [1] for GT, - 0: Disable; <b>1: Enable</b>. [2] for SA, <b>0: Disable</b>; 1: Enable. [3] through - [5] are Reserved. + Enable/Disable CEP (Current Excursion Protection) Support. 0: Disable; <b>1: Enable</b>. + [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. $EN_DIS **/ UINT8 CepEnable[6]; diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h index e30f626b43f4..c7cb725820a7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h @@ -813,7 +813,7 @@ typedef struct { **/ UINT8 Reserved17; -/** Offset 0x04D0 - Pointer of ChipsetInit Binary +/** Offset 0x04D0 - Pointer to ChipsetInit Binary ChipsetInit Binary Pointer. **/ UINT32 ChipsetInitBinPtr; |