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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2018-12-25 15:01:06 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-07 11:01:07 +0000 |
| commit | b6fe0489100c7b57f36bafa2ed142d7dc1ce10ea (patch) | |
| tree | 7fdfef49b7f2bdbdc9004f4dc8225e24fd8b3ca4 | |
| parent | b544c000565f928813299d0ea19dcae88ac7961e (diff) | |
| download | coreboot-b6fe0489100c7b57f36bafa2ed142d7dc1ce10ea.tar.gz coreboot-b6fe0489100c7b57f36bafa2ed142d7dc1ce10ea.tar.bz2 coreboot-b6fe0489100c7b57f36bafa2ed142d7dc1ce10ea.zip | |
mb/google/hatch: Enable touch panel support
Following changes are done to enable touch screen support on hatch
1. Enable I2C1 device at 400Khz at 3.3V
2. Configure GPIO for touch screen
3. Add ACPI entry for ELAN touch panel
4. update GPIO table with not connected GPIO pins for panel
BUG=b:120914069
BRANCH=none
TEST=check if code compiles with changes.
Change-Id: I8dab07dad4cb197865bb9cf0e8da240810fcfabe
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 20 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/gpio.c | 14 |
2 files changed, 31 insertions, 3 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index a3d0bc68363f..040d98d7f75a 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -25,6 +25,7 @@ chip soc/intel/cannonlake #| | for TPM communication | #| | before memory is up | #| I2C0 | Touchpad | + #| I2C1 | Touch screen | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { @@ -34,6 +35,9 @@ chip soc/intel/cannonlake .i2c[0] = { .speed = I2C_SPEED_FAST, }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, }" # FSP configuration @@ -167,7 +171,21 @@ chip soc/intel/cannonlake device i2c 15 on end end end # I2C #0 - device pci 15.1 off end # I2C #1 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device i2c 49 on end + end + end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 8d6968266864..e855fed9fff9 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -31,6 +31,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* TOUCHSCREEN_DIS_L */ + PAD_CFG_GPO(GPP_C4, 0, DEEP), /* GPP_C11_TP => NC */ PAD_NC(GPP_C11, DN_20K), /* GPP_C10_TP => NC */ @@ -39,12 +41,20 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TRACKPAD_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT), + /* PCH_I2C_TOUCHSCREEN_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* PCH_I2C_TOUCHSCREEN_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT), /* EC_IN_RW_OD */ PAD_CFG_GPI(GPP_C22, NONE, DEEP), + /* TOUCHSCREEN_RST_L */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), + /* TOUCHSCREEN_INT_L */ + PAD_CFG_GPI_APIC(GPP_D16, NONE, DEEP, LEVEL, INVERT), /* SATAGP1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), /* M2_SSD_PE_WAKE_ODL */ |