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| author | Weimin Wu <wuweimin@huaqin.corp-partner.google.com> | 2023-12-18 10:16:38 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-19 13:35:18 +0000 |
| commit | b8fd150da64a54f33971a0a524ec4364eadbce12 (patch) | |
| tree | 124035e45964663535210b96cfec441bc376d6f2 | |
| parent | 0f98655b37d32f0a8c7f778e2683ea6c595ee88d (diff) | |
| download | coreboot-b8fd150da64a54f33971a0a524ec4364eadbce12.tar.gz coreboot-b8fd150da64a54f33971a0a524ec4364eadbce12.tar.bz2 coreboot-b8fd150da64a54f33971a0a524ec4364eadbce12.zip | |
mb/google/nissa/var/anraggar: Use GPP_D15 to control AVDD and AFVDD
For EVT SCH:
1. Use GPP_D15 to control AVDD and AFVDD simultaneously for MIPI Camera.
2. Delay reset for 5ms when device power on.
BUG=b:312663347
TEST=1. Google Camera app working
2. Passed EA verified
Change-Id: I880fb309fcef006090e2849fa6c3a0d472851851
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/anraggar/overridetree.cb | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index 8d75381d18f6..a95c763d1acf 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -262,16 +262,17 @@ chip soc/intel/alderlake register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" - register "gpio_panel.gpio[0].gpio_num" = "GPP_F18" # EN_PP2800_WCAM_X + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1200_WCAM_X register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L #_ON - register "on_seq.ops_cnt" = "4" + register "on_seq.ops_cnt" = "5" register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" - register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" #_OFF register "off_seq.ops_cnt" = "4" |