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author | T Michael Turney <mturney@codeaurora.org> | 2021-03-18 09:16:44 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-15 19:07:56 +0000 |
commit | b97e6f713e1e2891b7ea8b76b34cfb24a2d74f64 (patch) | |
tree | b7d3cdc3e7c6977c3484ba41d4492d6b67d70238 | |
parent | 0c9eb3153386f9a3e70f3777df7e036a6c6249a3 (diff) | |
download | coreboot-b97e6f713e1e2891b7ea8b76b34cfb24a2d74f64.tar.gz coreboot-b97e6f713e1e2891b7ea8b76b34cfb24a2d74f64.tar.bz2 coreboot-b97e6f713e1e2891b7ea8b76b34cfb24a2d74f64.zip |
herobrine: sc7280: Provide initial mainboard support
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Change-Id: I428cf1a461ee63215f5683abbfed90202d1b2a88
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
-rw-r--r-- | src/mainboard/google/herobrine/Kconfig | 42 | ||||
-rw-r--r-- | src/mainboard/google/herobrine/Kconfig.name | 12 | ||||
-rw-r--r-- | src/mainboard/google/herobrine/Makefile.inc | 11 | ||||
-rw-r--r-- | src/mainboard/google/herobrine/board.h | 11 | ||||
-rw-r--r-- | src/mainboard/google/herobrine/board_info.txt | 6 | ||||
-rw-r--r-- | src/mainboard/google/herobrine/boardid.c | 25 | ||||
-rw-r--r-- | src/mainboard/google/herobrine/bootblock.c | 9 | ||||
-rw-r--r-- | src/mainboard/google/herobrine/chromeos.c | 15 | ||||
-rw-r--r-- | src/mainboard/google/herobrine/chromeos.fmd | 41 | ||||
-rw-r--r-- | src/mainboard/google/herobrine/devicetree.cb | 5 | ||||
-rw-r--r-- | src/mainboard/google/herobrine/mainboard.c | 19 | ||||
-rw-r--r-- | src/mainboard/google/herobrine/reset.c | 11 | ||||
-rw-r--r-- | src/mainboard/google/herobrine/romstage.c | 10 |
13 files changed, 217 insertions, 0 deletions
diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig new file mode 100644 index 000000000000..eb1e98624638 --- /dev/null +++ b/src/mainboard/google/herobrine/Kconfig @@ -0,0 +1,42 @@ +config BOARD_GOOGLE_HEROBRINE_COMMON # Umbrella option to be selected by variants + def_bool n + +if BOARD_GOOGLE_HEROBRINE_COMMON + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select COMMON_CBFS_SPI_WRAPPER + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_RTC + select EC_GOOGLE_CHROMEEC_SPI + select RTC + select SOC_QUALCOMM_SC7280 + select SPI_FLASH + select SPI_FLASH_WINBOND + select MAINBOARD_HAS_CHROMEOS + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select VBOOT_MOCK_SECDATA + +config MAINBOARD_DIR + string + default "google/herobrine" + +config MAINBOARD_VENDOR + string + default "Google" + + +########################################################## +#### Update below when adding a new derivative board. #### +########################################################## + +config MAINBOARD_PART_NUMBER + string + default "Herobrine" if BOARD_GOOGLE_HEROBRINE + +endif # BOARD_GOOGLE_HEROBRINE_COMMON diff --git a/src/mainboard/google/herobrine/Kconfig.name b/src/mainboard/google/herobrine/Kconfig.name new file mode 100644 index 000000000000..51d102ac35f5 --- /dev/null +++ b/src/mainboard/google/herobrine/Kconfig.name @@ -0,0 +1,12 @@ +comment "Herobrine" + +if USE_QC_BLOBS + +config BOARD_GOOGLE_HEROBRINE + bool "-> Herobrine" + select BOARD_GOOGLE_HEROBRINE_COMMON + +endif + +comment "(Herobrine requires 'Allow QC blobs repository')" + depends on !USE_QC_BLOBS diff --git a/src/mainboard/google/herobrine/Makefile.inc b/src/mainboard/google/herobrine/Makefile.inc new file mode 100644 index 000000000000..553634c29c37 --- /dev/null +++ b/src/mainboard/google/herobrine/Makefile.inc @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +all-y += boardid.c +all-y += chromeos.c +all-y += reset.c + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/google/herobrine/board.h b/src/mainboard/google/herobrine/board.h new file mode 100644 index 000000000000..c91a23898711 --- /dev/null +++ b/src/mainboard/google/herobrine/board.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _COREBOOT_SRC_MAINBOARD_GOOGLE_HEROBRINE_BOARD_H_ +#define _COREBOOT_SRC_MAINBOARD_GOOGLE_HEROBRINE_BOARD_H_ + +#include <boardid.h> +#include <gpio.h> + +void setup_chromeos_gpios(void); + +#endif /* _COREBOOT_SRC_MAINBOARD_GOOGLE_HEROBRINE_BOARD_H_ */ diff --git a/src/mainboard/google/herobrine/board_info.txt b/src/mainboard/google/herobrine/board_info.txt new file mode 100644 index 000000000000..a670d6ecad4c --- /dev/null +++ b/src/mainboard/google/herobrine/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Herobrine Qualcomm sc7280 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/herobrine/boardid.c b/src/mainboard/google/herobrine/boardid.c new file mode 100644 index 000000000000..eecbeab087ec --- /dev/null +++ b/src/mainboard/google/herobrine/boardid.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <gpio.h> + +uint32_t board_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; + + return id; +} + +uint32_t ram_code(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; + + return id; +} + +uint32_t sku_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; + + return id; +} diff --git a/src/mainboard/google/herobrine/bootblock.c b/src/mainboard/google/herobrine/bootblock.c new file mode 100644 index 000000000000..05e53a64bbc5 --- /dev/null +++ b/src/mainboard/google/herobrine/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include "board.h" + +void bootblock_mainboard_init(void) +{ + setup_chromeos_gpios(); +} diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c new file mode 100644 index 000000000000..c46bf7c2ad7d --- /dev/null +++ b/src/mainboard/google/herobrine/chromeos.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot/coreboot_tables.h> +#include <bootmode.h> +#include "board.h" + +void setup_chromeos_gpios(void) +{ + +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + +} diff --git a/src/mainboard/google/herobrine/chromeos.fmd b/src/mainboard/google/herobrine/chromeos.fmd new file mode 100644 index 000000000000..a44a638e98d1 --- /dev/null +++ b/src/mainboard/google/herobrine/chromeos.fmd @@ -0,0 +1,41 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# TODO: update for Herobrine +FLASH@0x0 8M { + WP_RO 4M { + RO_SECTION 0x3c4000 { + BOOTBLOCK 96K + COREBOOT(CBFS) + FMAP@0x3c0000 0x1000 + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 228K + RO_DDR_TRAINING(PRESERVE) 8K + RO_LIMITS_CFG(PRESERVE) 4K + } + + RW_VPD(PRESERVE) 32K + RW_NVRAM(PRESERVE) 16K + RW_DDR_TRAINING(PRESERVE) 8K + RW_LIMITS_CFG(PRESERVE) 4K + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA + } + + RW_SECTION_A 1280K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + + + RW_SECTION_B 1280K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + + RW_LEGACY(CBFS) +} diff --git a/src/mainboard/google/herobrine/devicetree.cb b/src/mainboard/google/herobrine/devicetree.cb new file mode 100644 index 000000000000..e23782facccf --- /dev/null +++ b/src/mainboard/google/herobrine/devicetree.cb @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/qualcomm/sc7280 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c new file mode 100644 index 000000000000..365fad41aa8b --- /dev/null +++ b/src/mainboard/google/herobrine/mainboard.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <bootblock_common.h> + +static void mainboard_init(struct device *dev) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/herobrine/reset.c b/src/mainboard/google/herobrine/reset.c new file mode 100644 index 000000000000..9b5810f20bb1 --- /dev/null +++ b/src/mainboard/google/herobrine/reset.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/google/chromeec/ec.h> +#include <reset.h> + +/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage), + but this works well enough for our purposes. */ +void do_board_reset(void) +{ + google_chromeec_reboot(0, EC_REBOOT_COLD, 0); +} diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c new file mode 100644 index 000000000000..8844f18e2e28 --- /dev/null +++ b/src/mainboard/google/herobrine/romstage.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/stages.h> +#include <soc/qclib_common.h> + +void platform_romstage_main(void) +{ + /* QCLib: DDR init & train */ + qclib_load_and_run(); +} |