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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-09-07 11:23:40 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-09 14:40:37 +0000 |
| commit | c2d0a494a3a60e14edb77bba3ee9736d49c4e531 (patch) | |
| tree | 1bd3d734b4a19eab8eb9f0e8c70c4354ae840b15 | |
| parent | efebedd3fb73d0c35529cfb74e1982bc2a0e2e2a (diff) | |
| download | coreboot-c2d0a494a3a60e14edb77bba3ee9736d49c4e531.tar.gz coreboot-c2d0a494a3a60e14edb77bba3ee9736d49c4e531.tar.bz2 coreboot-c2d0a494a3a60e14edb77bba3ee9736d49c4e531.zip | |
intel/xeon_sp/cpx: Hook up public microcode release
Change-Id: I7e575cb17e2004bd931f4fa1d05f17c4cdca29ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | Documentation/mainboard/ocp/deltalake.md | 3 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/Makefile.inc | 2 |
3 files changed, 4 insertions, 2 deletions
diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index 4510866d8f89..a2b61b4596de 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -24,7 +24,8 @@ Delta Lake server OSF solution requires: - FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package) is not yet available to the public. It will be made public soon by Intel with redistributable license. -- Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git. +- Microcode: Available through github.com/intel/Intel-Linux-Processor-Microcode-Data-Files. + coreboot.org mirrors this repo and by default the correct binary is included. - ME binary: Ignition binary will be made public soon by Intel with redistributable license. - ACM binaries: only required for CBnT enablement. Available under NDA with Intel. diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 51fc927fc0f4..4e3a7967fcb4 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -4,7 +4,6 @@ if SOC_INTEL_COOPERLAKE_SP config SOC_SPECIFIC_OPTIONS def_bool y - select MICROCODE_BLOB_NOT_HOOKED_UP config FSP_HEADER_PATH string "Location of FSP headers" diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 4d494b54664e..ac8d837322e5 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -17,4 +17,6 @@ ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-0b + endif ## CONFIG_SOC_INTEL_COOPERLAKE_SP |