src: Use of device_t is deprecated

Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

35 files changed, 109 insertions, 104 deletions

diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c
index 472adfc1a017..75e18208239e 100644
--- a/src/device/hypertransport.c
+++ b/src/device/hypertransport.c
@@ -34,9 +34,9 @@ struct ht_link {
 	unsigned char ctrl_off, config_off, freq_off, freq_cap_off;
 };
 
-static device_t ht_scan_get_devs(device_t *old_devices)
+static struct device *ht_scan_get_devs(struct device **old_devices)
 {
-	device_t first, last;
+	struct device *first, *last;
 
 	first = *old_devices;
 	last = first;
@@ -53,7 +53,7 @@ static device_t ht_scan_get_devs(device_t *old_devices)
 	}
 
 	if (first) {
-		device_t child;
+		struct device *child;
 
 		/* Unlink the chain from the list of old devices. */
 		*old_devices = last->sibling;
@@ -73,7 +73,7 @@ static device_t ht_scan_get_devs(device_t *old_devices)
 	return first;
 }
 
-static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos)
+static int ht_setup_link(struct ht_link *prev, struct device *dev, unsigned pos)
 {
 	struct ht_link cur[1];
 	int linkb_to_host;
@@ -256,7 +256,7 @@ static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_d
 	 * optimize link.
 	 */
 	unsigned int next_unitid, last_unitid, min_unitid, max_unitid;
-	device_t old_devices, dev, func, last_func = 0;
+	struct device *old_devices, *dev, *func, *last_func = NULL;
 	struct ht_link prev;
 	int ht_dev_num = 0;
 
@@ -271,7 +271,7 @@ static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_d
 	 */
 	unsigned int real_last_unitid = 0, end_used = 0;
 	u8 real_last_pos = 0;
-	device_t real_last_dev = NULL;
+	struct device *real_last_dev = NULL;
 #endif
 
 	/* Restore the hypertransport chain to it's uninitialized state. */
@@ -458,7 +458,7 @@ end_of_chain:
 	 * a problem in devicetree.cb.
 	 */
 	if (old_devices) {
-		device_t left;
+		struct device *left;
 		for (left = old_devices; left; left = left->sibling)
 			printk(BIOS_DEBUG, "%s\n", dev_path(left));
 
diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c
index 96f4d703a4e6..75f3357c1cdd 100644
--- a/src/drivers/net/ne2k.c
+++ b/src/drivers/net/ne2k.c
@@ -273,7 +273,11 @@ static void ns8390_reset(unsigned int eth_nic_base)
 
 int ne2k_init(unsigned int eth_nic_base) {
 
-	device_t dev;
+#ifdef __SIMPLE_DEVICE__
+	pci_devfn_t dev;
+#else
+	struct device *dev;
+#endif
 	unsigned char c;
 
 	/* Power management controller */
diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c
index 3bdeeebadcac..a61779cc7a95 100644
--- a/src/drivers/usb/pci_ehci.c
+++ b/src/drivers/usb/pci_ehci.c
@@ -37,7 +37,8 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
 #ifdef __SIMPLE_DEVICE__
 	pci_devfn_t dev = dbg_dev;
 #else
-	device_t dev = dev_find_slot(PCI_DEV2SEGBUS(dbg_dev), PCI_DEV2DEVFN(dbg_dev));
+	struct device *dev = dev_find_slot(PCI_DEV2SEGBUS(dbg_dev),
+					   PCI_DEV2DEVFN(dbg_dev));
 #endif
 
 	u32 class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
@@ -123,7 +124,8 @@ u8 *pci_ehci_base_regs(pci_devfn_t sdev)
 #ifdef __SIMPLE_DEVICE__
 	u8 *base = (u8 *)(pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f);
 #else
-	device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev));
+	struct device *dev = dev_find_slot(PCI_DEV2SEGBUS(sdev),
+					   PCI_DEV2DEVFN(sdev));
 	u8 *base = (u8 *)(pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f);
 #endif
 	return base + HC_LENGTH(read32(base));
diff --git a/src/include/device/cardbus.h b/src/include/device/cardbus.h
index 45ae24f00881..4443c155db30 100644
--- a/src/include/device/cardbus.h
+++ b/src/include/device/cardbus.h
@@ -5,8 +5,8 @@
 
 #include <device/device.h>
 
-void cardbus_read_resources(device_t dev);
-void cardbus_enable_resources(device_t dev);
+void cardbus_read_resources(struct device *dev);
+void cardbus_enable_resources(struct device *dev);
 
 extern struct device_operations default_cardbus_ops_bus;
 
diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h
index e7f212092ed5..0f1420a0133a 100644
--- a/src/include/device/pciexp.h
+++ b/src/include/device/pciexp.h
@@ -17,9 +17,9 @@ enum aspm_type {
 void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
 			     unsigned int max_devfn);
 
-void pciexp_scan_bridge(device_t dev);
+void pciexp_scan_bridge(struct device *dev);
 
 extern struct device_operations default_pciexp_ops_bus;
 
-unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap);
+unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap);
 #endif /* DEVICE_PCIEXP_H */
diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h
index 024c548b3eaf..ca482d26acdd 100644
--- a/src/include/device/pcix.h
+++ b/src/include/device/pcix.h
@@ -2,7 +2,7 @@
 #define DEVICE_PCIX_H
 /* (c) 2005 Linux Networx GPL see COPYING for details */
 
-void pcix_scan_bridge(device_t dev);
+void pcix_scan_bridge(struct device *dev);
 
 const char *pcix_speed(u16 sstatus);
 
diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c
index 80c926b1e372..e1e1a42895e0 100644
--- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c
+++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c
@@ -14,13 +14,13 @@
 #include <device/pnp_def.h>
 
 #define SCH4307_CONFIG_PORT     0x162e
-static inline void shc4307_enter_ext_func_mode(device_t dev)
+static inline void shc4307_enter_ext_func_mode(pnp_devfn_t dev)
 {
 	unsigned port = dev >> 8;
 	outb(0x55, port);
 }
 
-static inline void shc4307_exit_ext_func_mode(device_t dev)
+static inline void shc4307_exit_ext_func_mode(pnp_devfn_t dev)
 {
 	unsigned port = dev >> 8;
 	outb(0xaa, port);
diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c
index e67a127cf4e2..eaea725360c9 100644
--- a/src/northbridge/amd/amdfam10/acpi.c
+++ b/src/northbridge/amd/amdfam10/acpi.c
@@ -28,7 +28,7 @@
 
 unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint)
 {
-	device_t cpu;
+	struct device *cpu;
 	int cpu_index = 0;
 
 	for (cpu = all_devices; cpu; cpu = cpu->next) {
@@ -47,7 +47,7 @@ unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 l
 
 unsigned long acpi_create_srat_lapics(unsigned long current)
 {
-	device_t cpu;
+	struct device *cpu;
 	int cpu_index = 0;
 
 	for (cpu = all_devices; cpu; cpu = cpu->next) {
@@ -193,7 +193,7 @@ void update_ssdtx(void *ssdtx, int i)
 
 }
 
-void northbridge_acpi_write_vars(device_t device)
+void northbridge_acpi_write_vars(struct device *device)
 {
 	/*
 	 * If more than one physical CPU is installed, northbridge_acpi_write_vars()
@@ -326,7 +326,7 @@ void northbridge_acpi_write_vars(device_t device)
 	acpigen_pop_len();
 }
 
-unsigned long northbridge_write_acpi_tables(device_t device,
+unsigned long northbridge_write_acpi_tables(struct device *device,
 					    unsigned long current,
 					    struct acpi_rsdp *rsdp)
 {
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 3e34a25ae8bf..b744e96562c1 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -987,7 +987,7 @@ extern struct sys_info sysinfo_car;
 #endif
 */
 #ifndef __PRE_RAM__
-device_t get_node_pci(u32 nodeid, u32 fn);
+struct device *get_node_pci(u32 nodeid, u32 fn);
 #endif
 
 #ifdef __PRE_RAM__
@@ -1021,10 +1021,10 @@ BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List);
 struct acpi_rsdp;
 
 #ifndef __SIMPLE_DEVICE__
-unsigned long northbridge_write_acpi_tables(device_t device,
+unsigned long northbridge_write_acpi_tables(struct device *device,
 					    unsigned long start,
 					    struct acpi_rsdp *rsdp);
-void northbridge_acpi_write_vars(device_t device);
+void northbridge_acpi_write_vars(struct device *device);
 #endif
 
 #endif /* AMDFAM10_H */
diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c
index 916111caadeb..37b14927fa75 100644
--- a/src/northbridge/amd/amdfam10/ht_config.c
+++ b/src/northbridge/amd/amdfam10/ht_config.c
@@ -26,7 +26,7 @@
 struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
 {
 	struct dram_base_mask_t d;
-	device_t dev = __f1_dev[0];
+	struct device *dev = __f1_dev[0];
 
 	u32 temp;
 	temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
@@ -57,7 +57,7 @@ void set_config_map_reg(struct bus *link)
 	tempreg |= (busn_max << 24)|(busn_min << 16)|(linkn << 8);
 
 	for (i = 0; i < sysconf.nodes; i++) {
-		device_t dev = __f1_dev[i];
+		struct device *dev = __f1_dev[i];
 		pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg);
 	}
 }
@@ -68,7 +68,7 @@ void clear_config_map_reg(struct bus *link)
 	u32 ht_c_index = get_ht_c_index(link);
 
 	for (i = 0; i < sysconf.nodes; i++) {
-		device_t dev = __f1_dev[i];
+		struct device *dev = __f1_dev[i];
 		pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
 	}
 }
@@ -190,8 +190,8 @@ void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
 }
 
 
-void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
-				u32 io_min, u32 io_max)
+void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
+		     u32 io_min, u32 io_max)
 {
 	u32 i;
 	u32 tempreg;
diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h
index 75626fa0152e..748a9818c190 100644
--- a/src/northbridge/amd/amdfam10/ht_config.h
+++ b/src/northbridge/amd/amdfam10/ht_config.h
@@ -19,8 +19,8 @@
 typedef struct amdfam10_sysconf_t sys_info_conf_t;
 
 /* FIXME */
-u32 amdfam10_nodeid(device_t dev);
-extern device_t __f1_dev[];
+u32 amdfam10_nodeid(struct device *dev);
+extern struct device *__f1_dev[];
 
 struct dram_base_mask_t {
 	u32 base; //[47:27] at [28:8]
@@ -46,8 +46,8 @@ void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
 u32 get_io_addr_index(u32 nodeid, u32 linkn);
 u32 get_mmio_addr_index(u32 nodeid, u32 linkn);
 
-void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
-				u32 io_min, u32 io_max);
+void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
+		     u32 io_min, u32 io_max);
 
 void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes);
 
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
index 7cd9bff694db..028f6af46014 100644
--- a/src/northbridge/amd/amdfam10/misc_control.c
+++ b/src/northbridge/amd/amdfam10/misc_control.c
@@ -49,7 +49,7 @@
  * implemented in a way to NOT DOING legacy VGA resource allocation on
  * purpose :-(.
  */
-static void mcf3_read_resources(device_t dev)
+static void mcf3_read_resources(struct device *dev)
 {
 	struct resource *resource;
 	unsigned char gart;
@@ -75,14 +75,14 @@ static void mcf3_read_resources(device_t dev)
 	}
 }
 
-static void set_agp_aperture(device_t dev, uint32_t pci_id)
+static void set_agp_aperture(struct device *dev, uint32_t pci_id)
 {
 	uint32_t dword;
 	struct resource *resource;
 
 	resource = probe_resource(dev, 0x94);
 	if (resource) {
-		device_t pdev;
+		struct device *pdev;
 		u32 gart_base, gart_acr;
 
 		/* Remember this resource has been stored */
@@ -117,7 +117,7 @@ static void set_agp_aperture(device_t dev, uint32_t pci_id)
 	}
 }
 
-static void mcf3_set_resources_fam10h(device_t dev)
+static void mcf3_set_resources_fam10h(struct device *dev)
 {
 	/* Set the gart aperture */
 	set_agp_aperture(dev, 0x1203);
@@ -126,7 +126,7 @@ static void mcf3_set_resources_fam10h(device_t dev)
 	pci_dev_set_resources(dev);
 }
 
-static void mcf3_set_resources_fam15h_model10(device_t dev)
+static void mcf3_set_resources_fam15h_model10(struct device *dev)
 {
 	/* Set the gart aperture */
 	set_agp_aperture(dev, 0x1403);
@@ -135,7 +135,7 @@ static void mcf3_set_resources_fam15h_model10(device_t dev)
 	pci_dev_set_resources(dev);
 }
 
-static void mcf3_set_resources_fam15h(device_t dev)
+static void mcf3_set_resources_fam15h(struct device *dev)
 {
 	/* Set the gart aperture */
 	set_agp_aperture(dev, 0x1603);
diff --git a/src/northbridge/amd/amdfam10/northbridge.h b/src/northbridge/amd/amdfam10/northbridge.h
index 68b3f1d573bd..69d7415b226d 100644
--- a/src/northbridge/amd/amdfam10/northbridge.h
+++ b/src/northbridge/amd/amdfam10/northbridge.h
@@ -16,7 +16,7 @@
 #ifndef NORTHBRIDGE_AMD_AMDFAM10_H
 #define NORTHBRIDGE_AMD_AMDFAM10_H
 
-u32 amdfam10_scan_root_bus(device_t root, u32 max);
+u32 amdfam10_scan_root_bus(struct device *root, u32 max);
 void get_pci1234(void);
 
 #endif /* NORTHBRIDGE_AMD_AMDFAM10_H */
diff --git a/src/northbridge/amd/amdfam10/util.c b/src/northbridge/amd/amdfam10/util.c
index 4cce7f8bf757..4bcb11d04ad4 100644
--- a/src/northbridge/amd/amdfam10/util.c
+++ b/src/northbridge/amd/amdfam10/util.c
@@ -189,7 +189,7 @@ static void showmmio(int level, u8 which, u32 base, u32 lim)
  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
  *            raw config space.
  */
-static void showalldram(int level, device_t dev)
+static void showalldram(int level, struct device *dev)
 {
 	u8 reg;
 	for (reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) {
@@ -207,7 +207,7 @@ static void showalldram(int level, device_t dev)
  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
  *            raw config space.
  */
-static void showallmmio(int level, device_t dev)
+static void showallmmio(int level, struct device *dev)
 {
 	u8 reg;
 	for (reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) {
@@ -225,7 +225,7 @@ static void showallmmio(int level, device_t dev)
  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
  *            raw config space.
  */
-static void showallpciio(int level, device_t dev)
+static void showallpciio(int level, struct device *dev)
 {
 	u8 reg;
 	for (reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) {
@@ -243,7 +243,7 @@ static void showallpciio(int level, device_t dev)
  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
  *            raw config space.
  */
-static void showallconfig(int level, device_t dev)
+static void showallconfig(int level, struct device *dev)
 {
 	u8 reg;
 	for (reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) {
@@ -260,7 +260,7 @@ static void showallconfig(int level, device_t dev)
  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
  *            raw config space.
  */
-void showallroutes(int level, device_t dev)
+void showallroutes(int level, struct device *dev)
 {
 	showalldram(level, dev);
 	showallmmio(level, dev);
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 543b6911786b..b9ead3858a55 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -287,11 +287,11 @@ int sizeram(void)
 	return sizem;
 }
 
-static void enable_shadow(device_t dev)
+static void enable_shadow(struct device *dev)
 {
 }
 
-static void northbridge_init(device_t dev)
+static void northbridge_init(struct device *dev)
 {
 
 	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
@@ -348,11 +348,11 @@ static const struct pci_driver northbridge_driver __pci_driver = {
 
 #include <cbmem.h>
 
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
 {
 	int idx;
 	u32 tomk;
-	device_t mc_dev;
+	struct device *mc_dev;
 
 	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
@@ -371,7 +371,7 @@ static void pci_domain_set_resources(device_t dev)
 	assign_resources(dev->link_list);
 }
 
-static void pci_domain_enable(device_t dev)
+static void pci_domain_enable(struct device *dev)
 {
 	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
@@ -393,7 +393,7 @@ static struct device_operations pci_domain_ops = {
 	.enable = pci_domain_enable,
 };
 
-static void cpu_bus_init(device_t dev)
+static void cpu_bus_init(struct device *dev)
 {
 	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
diff --git a/src/northbridge/amd/pi/00630F01/iommu.c b/src/northbridge/amd/pi/00630F01/iommu.c
index 017269b492a6..0154acefbdfc 100644
--- a/src/northbridge/amd/pi/00630F01/iommu.c
+++ b/src/northbridge/amd/pi/00630F01/iommu.c
@@ -19,7 +19,7 @@
 #include <device/pci_ops.h>
 #include <lib.h>
 
-static void iommu_read_resources(device_t dev)
+static void iommu_read_resources(struct device *dev)
 {
 	struct resource *res;
 
@@ -35,7 +35,7 @@ static void iommu_read_resources(device_t dev)
 	res->flags = IORESOURCE_MEM;
 }
 
-static void iommu_set_resources(device_t dev)
+static void iommu_set_resources(struct device *dev)
 {
 	struct resource *res;
 
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 81843a421705..c7ababd216c7 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -50,7 +50,7 @@ static void tpm_enable(void)
 
 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {
-	device_t dev;
+	pci_devfn_t dev;
 
 	bootblock_systemagent_early_init();
 
@@ -75,7 +75,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 
 static void enable_pmcbar(void)
 {
-	device_t pmc = PCH_DEV_PMC;
+	pci_devfn_t pmc = PCH_DEV_PMC;
 
 	/* Set PMC base addresses and enable decoding. */
 	pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);
diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c
index 5b28db20e5b9..4acd7cbc2e7d 100644
--- a/src/soc/intel/apollolake/smihandler.c
+++ b/src/soc/intel/apollolake/smihandler.c
@@ -22,7 +22,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 
-int smihandler_soc_disable_busmaster(device_t dev)
+int smihandler_soc_disable_busmaster(pci_devfn_t dev)
 {
 	if (dev == PCH_DEV_PMC)
 		return 0;
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index ee9991759451..30e6d1d94be0 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -26,9 +26,9 @@
 
 #if defined(__SIMPLE_DEVICE__)
 
-static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0);
+static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0);
 
-static inline device_t get_pcu_dev(void)
+static inline pci_devfn_t get_pcu_dev(void)
 {
 	return pcu_dev;
 }
@@ -37,8 +37,8 @@ static inline device_t get_pcu_dev(void)
 #include <device/device.h>
 #include <device/pci.h>
 
-static device_t pcu_dev;
-static device_t get_pcu_dev(void)
+static struct device *pcu_dev;
+static struct device *get_pcu_dev(void)
 {
 	if (pcu_dev == NULL)
 		pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0));
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 683bf30b8678..c2227394b045 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -69,7 +69,7 @@ static void busmaster_disable_on_bus(int bus)
 	for (slot = 0; slot < 0x20; slot++) {
 		for (func = 0; func < 8; func++) {
 			u32 reg32;
-			device_t dev = PCI_DEV(bus, slot, func);
+			pci_devfn_t dev = PCI_DEV(bus, slot, func);
 
 			val = pci_read_config32(dev, PCI_VENDOR_ID);
 
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index 918e6d613445..c42b39859460 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -264,13 +264,12 @@ static void ich_set_bbar(uint32_t minaddr)
 
 static ich9_spi_regs *spi_regs(void)
 {
-	device_t dev;
 	uint32_t sbase;
 
 #ifdef __SMM__
-	dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
+	pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
 #else
-	dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+	struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
 #endif
 	pci_read_config_dword(dev, SBASE, &sbase);
 	sbase &= ~0x1ff;
diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index 18e655c1b37b..5f078dfbcfce 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -27,9 +27,9 @@
 
 #if defined(__SIMPLE_DEVICE__)
 
-static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0);
+static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0);
 
-static inline device_t get_pcu_dev(void)
+static inline pci_devfn_t get_pcu_dev(void)
 {
 	return pcu_dev;
 }
@@ -38,8 +38,8 @@ static inline device_t get_pcu_dev(void)
 #include <device/device.h>
 #include <device/pci.h>
 
-static device_t pcu_dev;
-static device_t get_pcu_dev(void)
+static struct device *pcu_dev;
+static struct device *get_pcu_dev(void)
 {
 	if (pcu_dev == NULL)
 		pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0));
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index 0f5c7c98c3fb..edbb7661094d 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -70,7 +70,7 @@ static void busmaster_disable_on_bus(int bus)
 	for (slot = 0; slot < 0x20; slot++) {
 		for (func = 0; func < 8; func++) {
 			u32 reg32;
-			device_t dev = PCI_DEV(bus, slot, func);
+			pci_devfn_t dev = PCI_DEV(bus, slot, func);
 
 			val = pci_read_config32(dev, PCI_VENDOR_ID);
 
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index b9e1627d15c5..f2d178d11a23 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -233,13 +233,12 @@ static void read_reg(void *src, void *value, uint32_t size)
 
 static ich9_spi_regs *spi_regs(void)
 {
-	device_t dev;
 	uint32_t sbase;
 
 #if ENV_SMM
-	dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
+	pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
 #else
-	dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+	struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
 #endif
 	if (!dev) {
 		printk(BIOS_ERR, "%s: PCI device not found", __func__);
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 8e4f7fd81e59..dc70a4f6c74a 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -52,7 +52,7 @@
 
 static void enable_p2sbbar(void)
 {
-	device_t dev = PCH_DEV_P2SB;
+	pci_devfn_t dev = PCH_DEV_P2SB;
 
 	/* Enable PCR Base address in PCH */
 	pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index c81e53435cb1..a2cd864cf34d 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -69,12 +69,12 @@ static struct {
 	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },
 };
 
-static uint8_t get_dev_revision(device_t dev)
+static uint8_t get_dev_revision(pci_devfn_t dev)
 {
 	return pci_read_config8(dev, PCI_REVISION_ID);
 }
 
-static uint16_t get_dev_id(device_t dev)
+static uint16_t get_dev_id(pci_devfn_t dev)
 {
 	return pci_read_config16(dev, PCI_DEVICE_ID);
 }
@@ -140,7 +140,7 @@ static void report_cpu_info(void)
 static void report_mch_info(void)
 {
 	int i;
-	device_t dev = SA_DEV_ROOT;
+	pci_devfn_t dev = SA_DEV_ROOT;
 	uint16_t mchid = get_dev_id(dev);
 	uint8_t mch_revision = get_dev_revision(dev);
 	const char *mch_type = "Unknown";
@@ -159,7 +159,7 @@ static void report_mch_info(void)
 static void report_pch_info(void)
 {
 	int i;
-	device_t dev = PCH_DEV_LPC;
+	pci_devfn_t dev = PCH_DEV_LPC;
 	uint16_t lpcid = get_dev_id(dev);
 	const char *pch_type = "Unknown";
 
@@ -176,7 +176,7 @@ static void report_pch_info(void)
 static void report_igd_info(void)
 {
 	int i;
-	device_t dev = SA_DEV_IGD;
+	pci_devfn_t dev = SA_DEV_IGD;
 	uint16_t igdid = get_dev_id(dev);
 	const char *igd_type = "Unknown";
 
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index ba010aaa600e..0ecc66df0275 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -35,7 +35,8 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void)
 	return &em64t101_smm_ops;
 }
 
-static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)
+static void pch_configure_endpoints(pci_devfn_t dev, int epmask_id,
+				    uint32_t mask)
 {
 	uint32_t reg32;
 
@@ -43,7 +44,7 @@ static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)
 	pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask);
 }
 
-static void disable_sideband_access(device_t dev)
+static void disable_sideband_access(pci_devfn_t dev)
 {
 	u8 reg8;
 	uint32_t mask;
@@ -60,7 +61,7 @@ static void disable_sideband_access(device_t dev)
 
 static void pch_disable_heci(void)
 {
-	device_t dev = PCH_DEV_P2SB;
+	pci_devfn_t dev = PCH_DEV_P2SB;
 	struct pcr_sbi_msg msg = {
 		.pid = PID_CSME0,
 		.offset = 0,
diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index 83330e6ba6f6..3c60ef2b34c8 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -255,7 +255,7 @@ static void setup_ied_area(struct smm_relocation_params *params)
 void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 				size_t *smm_save_state_size)
 {
-	device_t dev = SA_DEV_ROOT;
+	struct device *dev = SA_DEV_ROOT;
 
 	printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
 
diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c
index a5884122d609..33ecc0948877 100644
--- a/src/soc/intel/fsp_baytrail/pmutil.c
+++ b/src/soc/intel/fsp_baytrail/pmutil.c
@@ -35,8 +35,8 @@ static inline pci_devfn_t get_pcu_dev(void)
 #include <device/device.h>
 #include <device/pci.h>
 
-static device_t pcu_dev;
-static device_t get_pcu_dev(void)
+static struct device *pcu_dev;
+static struct device *get_pcu_dev(void)
 {
 	if (pcu_dev == NULL)
 		pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0));
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index 6787dcbe189e..d8b1d55397ef 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -259,7 +259,7 @@ static ich9_spi_regs *spi_regs(void)
 	pci_devfn_t dev;
 	dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
 #else
-	device_t dev;
+	struct device *dev;
 	dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
 #endif
 	pci_read_config_dword(dev, SBASE, &sbase);
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index 57a300c64b2c..96adfb5bdd29 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -49,7 +49,7 @@ static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
 }
 
 
-static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev,
+static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev,
 	u32 reg_pos, u32 mask, u32 val)
 {
 	u32 reg_old, reg;
@@ -100,7 +100,7 @@ static void get_cpu_rev(void)
 /*
 CIM NB_GetRevisionInfo()
 */
-static u8 get_nb_rev(device_t nb_dev)
+static u8 get_nb_rev(pci_devfn_t nb_dev)
 {
 	u8 reg;
 	reg = pci_read_config8(nb_dev, 0x8);	/* copy from CIM, can't find in doc */
@@ -148,7 +148,7 @@ void sr5650_htinit(void)
 	/*
 	 * About HT, it has been done in enumerate_ht_chain().
 	 */
-	device_t cpu_f0, sr5650_f0, clk_f1;
+	pci_devfn_t cpu_f0, sr5650_f0, clk_f1;
 	u32 reg;
 	u8 cpu_ht_freq, cpu_htfreq_max, ibias;
 	u8 sbnode;
@@ -277,7 +277,7 @@ void sr5650_htinit(void)
  */
 void sr5650_htinit_dect_and_enable_isochronous_link(void)
 {
-	device_t sr5650_f0;
+	pci_devfn_t sr5650_f0;
 	unsigned char iommu;
 
 	sr5650_f0 = PCI_DEV(0, 0, 0);
@@ -300,8 +300,8 @@ void sr5650_htinit_dect_and_enable_isochronous_link(void)
 
 void fam10_optimization(void)
 {
-	device_t cpu_f0, cpu_f2, cpu_f3;
-	device_t cpu1_f0, cpu1_f2, cpu1_f3;
+	pci_devfn_t cpu_f0, cpu_f2, cpu_f3;
+	pci_devfn_t cpu1_f0, cpu1_f2, cpu1_f3;
 	msr_t msr;
 	u32 val;
 
@@ -331,7 +331,7 @@ void fam10_optimization(void)
 /*****************************************
 * Compliant with CIM_33's ATINB_PCICFG_POR_TABLE
 *****************************************/
-static void sr5650_por_pcicfg_init(device_t nb_dev)
+static void sr5650_por_pcicfg_init(pci_devfn_t nb_dev)
 {
 	/* enable PCI Memory Access */
 	set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02);
@@ -357,7 +357,7 @@ static void sr5650_por_pcicfg_init(device_t nb_dev)
 * Compliant with CIM_33's ATINB_MISCIND_POR_TABLE
 * Compliant with CIM_33's MISC_INIT_TBL
 *****************************************/
-static void sr5650_por_misc_index_init(device_t nb_dev)
+static void sr5650_por_misc_index_init(pci_devfn_t nb_dev)
 {
 	unsigned char iommu;
 
@@ -455,9 +455,9 @@ static void sr5650_por_misc_index_init(device_t nb_dev)
 /*****************************************
 * Some setting is from rpr. Some is from CIMx.
 *****************************************/
-static void sr5650_por_htiu_index_init(device_t nb_dev)
+static void sr5650_por_htiu_index_init(pci_devfn_t nb_dev)
 {
-	device_t cpu_f0;
+	pci_devfn_t cpu_f0;
 
 	cpu_f0 = PCI_DEV(0, 0x18, 0);
 
@@ -505,7 +505,7 @@ static void sr5650_por_htiu_index_init(device_t nb_dev)
 * POR: Power On Reset
 * RPR: Register Programming Requirements
 *****************************************/
-static void sr5650_por_init(device_t nb_dev)
+static void sr5650_por_init(pci_devfn_t nb_dev)
 {
 	printk(BIOS_INFO, "sr5650_por_init\n");
 	/* ATINB_PCICFG_POR_TABLE, initialize the values for sr5650 PCI Config registers */
@@ -539,7 +539,7 @@ void sr5650_before_pci_init(void)
 */
 void sr5650_early_setup(void)
 {
-	device_t nb_dev = PCI_DEV(0, 0, 0);
+	pci_devfn_t nb_dev = PCI_DEV(0, 0, 0);
 	printk(BIOS_INFO, "sr5650_early_setup()\n");
 
 	/*ATINB_PrepareInit */
@@ -573,7 +573,7 @@ void sr5650_disable_pcie_bridge(void)
 {
 	u32 mask;
 	u32 reg;
-	device_t nb_dev = PCI_DEV(0, 0, 0);
+	pci_devfn_t nb_dev = PCI_DEV(0, 0, 0);
 
 	mask = (1 << 2) | (1 << 3); /*GPP1*/
 	mask |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/
diff --git a/src/superio/intel/i8900/i8900.h b/src/superio/intel/i8900/i8900.h
index 0312d41cbb51..3879a364238b 100644
--- a/src/superio/intel/i8900/i8900.h
+++ b/src/superio/intel/i8900/i8900.h
@@ -49,8 +49,8 @@
 #define I8900_UART_CLK_PREDIVIDE_26	0x02
 #define I8900_ENABLE_SIRQ		0x01
 
-void i8900_configure_uart_clk(device_t dev, u8 predivide);
-void i8900_enable_serial(device_t dev, u16 iobase);
-void i8900_enable_wdt(device_t dev, u16 iobase);
+void i8900_configure_uart_clk(pnp_devfn_t dev, u8 predivide);
+void i8900_enable_serial(pnp_devfn_t dev, u16 iobase);
+void i8900_enable_wdt(pnp_devfn_t dev, u16 iobase);
 
 #endif
diff --git a/src/superio/winbond/wpcd376i/early_serial.c b/src/superio/winbond/wpcd376i/early_serial.c
index 4845dd626ea0..115e097492aa 100644
--- a/src/superio/winbond/wpcd376i/early_serial.c
+++ b/src/superio/winbond/wpcd376i/early_serial.c
@@ -21,7 +21,7 @@
 #include <device/pnp_def.h>
 #include "wpcd376i.h"
 
-void wpcd376i_enable_serial(device_t dev, u16 iobase)
+void wpcd376i_enable_serial(pnp_devfn_t dev, u16 iobase)
 {
 	pnp_set_logical_device(dev);
 	pnp_set_enable(dev, 0);
diff --git a/src/superio/winbond/wpcd376i/superio.c b/src/superio/winbond/wpcd376i/superio.c
index 25012b08e832..c18b9e57f89e 100644
--- a/src/superio/winbond/wpcd376i/superio.c
+++ b/src/superio/winbond/wpcd376i/superio.c
@@ -24,7 +24,7 @@
 #include "chip.h"
 #include "wpcd376i.h"
 
-static void init(device_t dev)
+static void init(struct device *dev)
 {
 	if (!dev->enabled)
 		return;
diff --git a/src/superio/winbond/wpcd376i/wpcd376i.h b/src/superio/winbond/wpcd376i/wpcd376i.h
index b894e4e0c782..8d770b4384f1 100644
--- a/src/superio/winbond/wpcd376i/wpcd376i.h
+++ b/src/superio/winbond/wpcd376i/wpcd376i.h
@@ -30,6 +30,6 @@
 #define WPCD376I_KBCK	6	/* PS/2 keyboard */
 #define WPCD376I_GPIO	7	/* General Purpose I/O */
 
-void wpcd376i_enable_serial(device_t dev, u16 iobase);
+void wpcd376i_enable_serial(pnp_devfn_t dev, u16 iobase);
 
 #endif