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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-15 16:11:19 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-31 00:04:45 +0000 |
| commit | cbd4ee73d71648821a268ce5c700236a95ba6125 (patch) | |
| tree | 465e7ebbd2d0716450c527835fcf82859b2c49cf | |
| parent | 1b940d17a898aab3f5891c2c5c94d5881108ba07 (diff) | |
| download | coreboot-cbd4ee73d71648821a268ce5c700236a95ba6125.tar.gz coreboot-cbd4ee73d71648821a268ce5c700236a95ba6125.tar.bz2 coreboot-cbd4ee73d71648821a268ce5c700236a95ba6125.zip | |
cpu/intel/common: correct MSR for the Nominal Performance in CPPC
The "Nominal Performance" is not the same as the "Guaranteed
Performance", but is defined as the performance a processor can deliver
continously under ideal environmental conditions.
According to edk2, this is the "Maximum Non-Turbo Ratio", which needs to
be read from MSR_PLATFORM_INFO instead of IA32_HWP_CAPABILITIES.
Correct the entry in the CPPC package.
Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled
version
Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46464
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/cpu/intel/common/common_init.c | 16 | ||||
| -rw-r--r-- | src/include/cpu/intel/msr.h | 2 |
2 files changed, 11 insertions, 7 deletions
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 3ea8f36ea82d..c5f43ef22ea9 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -131,13 +131,6 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) config->regs[CPPC_HIGHEST_PERF] = msr; /* - * Nominal Performance -> Guaranteed Performance: - * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)}, - */ - msr.bit_offset = 8; - config->regs[CPPC_NOMINAL_PERF] = msr; - - /* * Lowest Nonlinear Performance -> Most Efficient Performance: * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)}, */ @@ -158,6 +151,15 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version) msr.bit_offset = 8; config->regs[CPPC_GUARANTEED_PERF] = msr; + msr.addrl = MSR_PLATFORM_INFO; + + /* + * Nominal Performance -> Maximum Non-Turbo Ratio: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0xce, 0x04,)}, + */ + msr.bit_offset = 8; + config->regs[CPPC_NOMINAL_PERF] = msr; + msr.addrl = IA32_HWP_REQUEST; /* diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index a2165f365aed..da0f0bb68d11 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -12,4 +12,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define TPR_UPDATES_DISABLE (1 << 10) +#define MSR_PLATFORM_INFO 0xce + #endif /* CPU_INTEL_MSR_H */ |