intel/smm/gen1: Use smm_subregion()

Change-Id: I371ed41f485b3143e47f091681198d6674928897
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34740
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 62 insertions, 107 deletions

diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 9b0175d82f2d..0a477bb6c69c 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -43,10 +43,8 @@
 
 
 struct smm_relocation_params {
-	u32 smram_base;
-	u32 smram_size;
-	u32 ied_base;
-	u32 ied_size;
+	uintptr_t ied_base;
+	size_t ied_size;
 	msr_t smrr_base;
 	msr_t smrr_mask;
 };
@@ -103,50 +101,31 @@ static void write_smrr(struct smm_relocation_params *relo_params)
 
 static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
+	uintptr_t tseg_base;
+	size_t tseg_size;
+
 	/* All range registers are aligned to 4KiB */
 	const u32 rmask = ~((1 << 12) - 1);
 
-	const u32 tsegmb = northbridge_get_tseg_base();
-	/* TSEG base is usually aligned down (to 8MiB). So we can't
-	   derive the TSEG size from the distance to GTT but use the
-	   configuration value instead. */
-	const u32 tseg_size = northbridge_get_tseg_size();
-
-	params->smram_base = tsegmb;
-	params->smram_size = tseg_size;
-	if (CONFIG_IED_REGION_SIZE != 0) {
-		ASSERT(params->smram_size > CONFIG_IED_REGION_SIZE);
-		params->smram_size -= CONFIG_IED_REGION_SIZE;
-		params->ied_base = tsegmb + tseg_size - CONFIG_IED_REGION_SIZE;
-		params->ied_size = CONFIG_IED_REGION_SIZE;
-	}
+	smm_region(&tseg_base, &tseg_size);
 
-	/* Adjust available SMM handler memory size. */
-	if (CONFIG(TSEG_STAGE_CACHE)) {
-		ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE);
-		params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
-	}
-
-	if (IS_ALIGNED(tsegmb, tseg_size)) {
-		/* SMRR has 32-bits of valid address aligned to 4KiB. */
-		struct cpuinfo_x86 c;
-
-		/* On model_6fx and model_1067x bits [0:11] on smrr_base
-		   are reserved */
-		get_fms(&c, cpuid_eax(1));
-		if (cpu_has_alternative_smrr())
-			params->smrr_base.lo = (params->smram_base & rmask);
-		else
-			params->smrr_base.lo = (params->smram_base & rmask)
-				| MTRR_TYPE_WRBACK;
-		params->smrr_base.hi = 0;
-		params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
-			| MTRR_PHYS_MASK_VALID;
-		params->smrr_mask.hi = 0;
-	} else {
+	if (!IS_ALIGNED(tseg_base, tseg_size)) {
 		printk(BIOS_WARNING,
 		       "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n");
+		return;
 	}
+
+	/* SMRR has 32-bits of valid address aligned to 4KiB. */
+	params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
+	params->smrr_base.hi = 0;
+	params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
+	params->smrr_mask.hi = 0;
+
+	/* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */
+	if (cpu_has_alternative_smrr())
+		params->smrr_base.lo &= ~rmask;
+
+	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
 }
 
 static void setup_ied_area(struct smm_relocation_params *params)
@@ -186,11 +165,11 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 
 	fill_in_relocation_params(&smm_reloc_params);
 
-	if (CONFIG_IED_REGION_SIZE != 0)
+	smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
+
+	if (smm_reloc_params.ied_size)
 		setup_ied_area(&smm_reloc_params);
 
-	*perm_smbase = smm_reloc_params.smram_base;
-	*perm_smsize = smm_reloc_params.smram_size;
 	*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
 }
 
@@ -221,7 +200,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 	printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
 
 	/* Make appropriate changes to the save state map. */
-	if (CONFIG_IED_REGION_SIZE != 0)
+	if (relo_params->ied_size)
 		printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
 		       smbase, iedbase);
 	else
@@ -235,7 +214,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 
 	/* Write EMRR and SMRR MSRs based on indicated support. */
 	mtrr_cap = rdmsr(MTRR_CAP_MSR);
-	if (!(mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0))
+	if (!(mtrr_cap.lo & SMRR_SUPPORTED))
 		return;
 
 	if (cpu_has_alternative_smrr())
diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h
index 5213bc909e45..cb196fcd82a5 100644
--- a/src/include/cpu/intel/smm_reloc.h
+++ b/src/include/cpu/intel/smm_reloc.h
@@ -23,8 +23,6 @@ struct ied_header {
 } __packed;
 
 /* These helpers are for performing SMM relocation. */
-u32 northbridge_get_tseg_base(void);
-u32 northbridge_get_tseg_size(void);
 void northbridge_write_smram(u8 smram);
 
 void smm_lock(void);
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 6e2f7037c2ba..7479a7834acb 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -23,9 +23,9 @@
 #include <device/pci_def.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <cbmem.h>
 #include <program_loading.h>
-#include <stage_cache.h>
 #include <cpu/intel/smm_reloc.h>
 #include "gm45.h"
 
@@ -84,7 +84,7 @@ u32 decode_tseg_size(u8 esmramc)
 	}
 }
 
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
 {
 	const pci_devfn_t dev = PCI_DEV(0, 0, 0);
 
@@ -107,7 +107,7 @@ u32 northbridge_get_tseg_base(void)
 	return tor;
 }
 
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
 {
 	const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
 	return decode_tseg_size(esmramc) << 10;
@@ -123,14 +123,10 @@ void *cbmem_top(void)
 	return (void *) top_of_ram;
 }
 
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	/* The stage cache lives at the end of the TSEG region.
-	 * The top of RAM is defined to be the TSEG base address.
-	 */
-	*size = CONFIG_SMM_RESERVED_SIZE;
-	*base = (void *)((uintptr_t)northbridge_get_tseg_base()
-		+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+	*start = northbridge_get_tseg_base();
+	*size = northbridge_get_tseg_size();
 }
 
 void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 8179f1788867..8207d06a5579 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -22,10 +22,10 @@
 #include "i945.h"
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <program_loading.h>
 #include <cpu/intel/smm_reloc.h>
 #include <stdint.h>
-#include <stage_cache.h>
 
 /* Decodes TSEG region size to bytes. */
 u32 decode_tseg_size(const u8 esmramc)
@@ -45,7 +45,7 @@ u32 decode_tseg_size(const u8 esmramc)
 	}
 }
 
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
 {
 	uintptr_t tom;
 
@@ -60,7 +60,7 @@ u32 northbridge_get_tseg_base(void)
 	return tom;
 }
 
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
 {
 	const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
 	return decode_tseg_size(esmramc);
@@ -89,14 +89,10 @@ u32 decode_igd_memory_size(const u32 gms)
 	return ggc2uma[gms] << 10;
 }
 
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	/* The stage cache lives at the end of the TSEG region.
-	 * The top of RAM is defined to be the TSEG base address.
-	 */
-	*size = CONFIG_SMM_RESERVED_SIZE;
-	*base = (void *)((uintptr_t)northbridge_get_tseg_base()
-		+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+	*start = northbridge_get_tseg_base();
+	*size = northbridge_get_tseg_size();
 }
 
 void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c
index 1687ddf78b4e..fd10542832fe 100644
--- a/src/northbridge/intel/nehalem/memmap.c
+++ b/src/northbridge/intel/nehalem/memmap.c
@@ -21,8 +21,8 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <program_loading.h>
-#include <stage_cache.h>
 #include <cpu/intel/smm_reloc.h>
 #include "nehalem.h"
 
@@ -33,12 +33,12 @@ static uintptr_t smm_region_start(void)
 	return tom;
 }
 
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
 {
-	return (u32)smm_region_start();
+	return smm_region_start();
 }
 
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
 {
 	return CONFIG_SMM_TSEG_SIZE;
 }
@@ -48,13 +48,10 @@ void *cbmem_top(void)
 	return (void *) smm_region_start();
 }
 
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	/* The stage cache lives at the end of TSEG region.
-	 * The top of RAM is defined to be the TSEG base address. */
-	*size = CONFIG_SMM_RESERVED_SIZE;
-	*base = (void *)((uintptr_t)northbridge_get_tseg_base() +
-			northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+	*start = northbridge_get_tseg_base();
+	*size = northbridge_get_tseg_size();
 }
 
 void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 9908f110cd16..b4fef6bc76ad 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -24,9 +24,9 @@
 #include <cbmem.h>
 #include <northbridge/intel/pineview/pineview.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <cpu/intel/smm_reloc.h>
 #include <stdint.h>
-#include <stage_cache.h>
 
 u8 decode_pciebar(u32 *const base, u32 *const len)
 {
@@ -116,13 +116,13 @@ static u32 decode_tseg_size(const u32 esmramc)
 	}
 }
 
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
 {
 	const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
 	return decode_tseg_size(esmramc);
 }
 
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
 {
 	return pci_read_config32(PCI_DEV(0, 0, 0), TSEG);
 }
@@ -139,14 +139,10 @@ void *cbmem_top(void)
 
 }
 
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	/* The stage cache lives at the end of the TSEG region.
-	 * The top of RAM is defined to be the TSEG base address.
-	 */
-	*size = CONFIG_SMM_RESERVED_SIZE;
-	*base = (void *)((uintptr_t)northbridge_get_tseg_base()
-		+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+	*start = northbridge_get_tseg_base();
+	*size = northbridge_get_tseg_size();
 }
 
 void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index fa29b3782bc1..95bf4584ed53 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -21,8 +21,8 @@
 #include <console/console.h>
 #include <cpu/intel/smm_reloc.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <program_loading.h>
-#include <stage_cache.h>
 #include "sandybridge.h"
 
 static uintptr_t smm_region_start(void)
@@ -37,23 +37,20 @@ void *cbmem_top(void)
 	return (void *) smm_region_start();
 }
 
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
 {
 	return ALIGN_DOWN(smm_region_start(), 1*MiB);
 }
 
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
 {
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	/* The stage cache lives at the end of TSEG region.
-	 * The top of RAM is defined to be the TSEG base address. */
-	*size = CONFIG_SMM_RESERVED_SIZE;
-	*base = (void *)((uintptr_t)northbridge_get_tseg_base() + northbridge_get_tseg_size()
-			- CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE);
+	*start = northbridge_get_tseg_base();
+	*size = northbridge_get_tseg_size();
 }
 
 void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 2f50768c460e..41e491200bdb 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -25,10 +25,10 @@
 #include <device/pci_def.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <program_loading.h>
 #include <cpu/intel/smm_reloc.h>
-#include <stage_cache.h>
 
 /** Decodes used Graphics Mode Select (GMS) to kilobytes. */
 u32 decode_igd_memory_size(const u32 gms)
@@ -112,13 +112,13 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
 	return 1;
 }
 
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
 {
 	const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
 	return decode_tseg_size(esmramc);
 }
 
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
 {
 	return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG);
 }
@@ -134,14 +134,10 @@ void *cbmem_top(void)
 	return (void *) top_of_ram;
 }
 
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	/* The stage cache lives at the end of the TSEG region.
-	 * The top of RAM is defined to be the TSEG base address.
-	 */
-	*size = CONFIG_SMM_RESERVED_SIZE;
-	*base = (void *)((uintptr_t)northbridge_get_tseg_base()
-		+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+	*start = northbridge_get_tseg_base();
+	*size = northbridge_get_tseg_size();
 }
 
 void fill_postcar_frame(struct postcar_frame *pcf)