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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-09-11 10:03:08 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2018-09-15 11:53:34 +0000 |
| commit | ded91fffb833823ea7d71654c1e10696eba0d419 (patch) | |
| tree | 34c720d4e0f5d8f794a61e8cda10e7c7939c0b5c | |
| parent | 694d18a6418bea102850e1695ad4d71fe831a113 (diff) | |
| download | coreboot-ded91fffb833823ea7d71654c1e10696eba0d419.tar.gz coreboot-ded91fffb833823ea7d71654c1e10696eba0d419.tar.bz2 coreboot-ded91fffb833823ea7d71654c1e10696eba0d419.zip | |
arch/riscv: Configure delegation only if S-mode is supported
On the FU540 the bootblock runs on a core without lesser privilege
modes, so the medeleg/mideleg CSRs are not implemented on that core,
leading to a CPU exception when these CSRs are accessed.
Configure medeleg/mideleg only if the misa register indicates that
S-mode is implemented on the executing RISC-V core.
Change-Id: Idad97e42bac2ff438dd233a5d125f93594505d63
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25791
Reviewed-by: Xiang Wang <wxjstz@126.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/arch/riscv/virtual_memory.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 3bee86865d48..5b35e811d94d 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> #include <arch/encoding.h> #include <stdint.h> #include <vm.h> @@ -52,11 +53,12 @@ void mstatus_init(void) // all other supervisor interrupts. set_csr(mie, MIP_MTIP | MIP_STIP | MIP_SSIP); - // Delegate supervisor timer and other interrupts - // to supervisor mode. - set_csr(mideleg, MIP_STIP | MIP_SSIP); - - set_csr(medeleg, delegate); + // Delegate supervisor timer and other interrupts to supervisor mode, + // if supervisor mode is supported. + if (supports_extension('S')) { + set_csr(mideleg, MIP_STIP | MIP_SSIP); + set_csr(medeleg, delegate); + } // Enable all user/supervisor-mode counters using // v1.10 register addresses. |