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| author | Subrata Banik <subratabanik@google.com> | 2021-12-27 10:49:19 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-01-16 13:34:19 +0000 |
| commit | e74ebcde38c78a4b81f621211d58c618ae1ad3a7 (patch) | |
| tree | 9e07bab47b6feeefb9ceb5f0eafc8d71163d0713 | |
| parent | a0d9ad322fe603d4d4cbccda9c7edcfbf0b13409 (diff) | |
| download | coreboot-e74ebcde38c78a4b81f621211d58c618ae1ad3a7.tar.gz coreboot-e74ebcde38c78a4b81f621211d58c618ae1ad3a7.tar.bz2 coreboot-e74ebcde38c78a4b81f621211d58c618ae1ad3a7.zip | |
soc/intel/common/cse: Add helper API for CSE SPI Protection Mode
This patch checks if CSE's spi protection mode is protected or
unprotected. Returns true if CSE's spi protection mode is protected,
otherwise false.
BUG=b:211954778
TEST=Able to build and boot brya with this change. Calling
`cse_is_hfs1_spi_protected()` in coreboot is able to provide
the SPI protection status.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I23f1a1c4b55d8da6e6fd0cf84bef86f49ce80cca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 16 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 6 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 05b67eed32fe..7d6fabaa9be1 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -257,6 +257,22 @@ bool cse_is_hfs1_com_soft_temp_disable(void) return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE); } +/* + * TGL HFSTS1.spi_protection_mode bit replaces the previous + * `manufacturing mode (mfg_mode)` without changing the offset and purpose + * of this bit. + * + * Using HFSTS1.mfg_mode to get the SPI protection status for all PCH. + * mfg_mode = 0 means SPI protection in on. + * mfg_mode = 1 means SPI is unprotected. + */ +bool cse_is_hfs1_spi_protected(void) +{ + union me_hfsts1 hfs1; + hfs1.data = me_read_config32(PCI_ME_HFSTS1); + return !hfs1.fields.mfg_mode; +} + bool cse_is_hfs3_fw_sku_lite(void) { union me_hfsts3 hfs3; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 68f1d3c2a81e..540dabc76c48 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -301,6 +301,12 @@ bool cse_is_hfs1_com_secover_mei_msg(void); bool cse_is_hfs1_com_soft_temp_disable(void); /* + * Checks CSE's spi protection mode is protected or unprotected. + * Returns true if CSE's spi protection mode is protected, otherwise false. + */ +bool cse_is_hfs1_spi_protected(void); + +/* * Checks CSE's Firmware SKU is Lite or not. * Returns true if CSE's Firmware SKU is Lite, otherwise false */ |