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| author | Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com> | 2021-07-06 22:28:02 +0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-11 20:15:10 +0000 |
| commit | e985d211fb1d975bbb5bee0ed2597c24ee05bd1e (patch) | |
| tree | 2c46340440c2ef80ca6dfae75a1dd7483305738f | |
| parent | c1de9e88e7edd85d2a4fe5b7f2f4a30ff4716a10 (diff) | |
| download | coreboot-e985d211fb1d975bbb5bee0ed2597c24ee05bd1e.tar.gz coreboot-e985d211fb1d975bbb5bee0ed2597c24ee05bd1e.tar.bz2 coreboot-e985d211fb1d975bbb5bee0ed2597c24ee05bd1e.zip | |
ppc64/arch/mmio.h: ignore HRMOR and inhibit cache
Change-Id: I9895fc0dcc0ab72151f3b2bde409c8556525433d
Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
| -rw-r--r-- | src/arch/ppc64/include/arch/mmio.h | 75 |
1 files changed, 67 insertions, 8 deletions
diff --git a/src/arch/ppc64/include/arch/mmio.h b/src/arch/ppc64/include/arch/mmio.h index 642804372785..c93e570d3e8f 100644 --- a/src/arch/ppc64/include/arch/mmio.h +++ b/src/arch/ppc64/include/arch/mmio.h @@ -5,38 +5,97 @@ #include <stdint.h> -/* NOTE: These are just stubs; if the architecture requires special - * care to avoid posted writes or cachelines, it is not yet done here. +/* NOTE: In some cases accesses to MMIO must be separated by eieio instruction + * to prevent reordering. This is not included in functions below (performance + * reasons) and must be called explicitly. Function eieio() is defined in io.h. */ static inline uint8_t read8(const volatile void *addr) { - return *(volatile uint8_t *)addr; + uint8_t val; + + /* Set bit to ignore HRMOR */ + addr = (const volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "lbzcix %0, 0, %1" : + "=r"(val) : "r"(addr)); + + return val; } static inline uint16_t read16(const volatile void *addr) { - return *(volatile uint16_t *)addr; + uint16_t val; + + /* Set bit to ignore HRMOR */ + addr = (const volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "lhzcix %0, 0, %1" : + "=r"(val) : "r"(addr)); + + return val; } static inline uint32_t read32(const volatile void *addr) { - return *(volatile uint32_t *)addr; + uint32_t val; + + /* Set bit to ignore HRMOR */ + addr = (const volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "lwzcix %0, 0, %1" : + "=r"(val) : "r"(addr)); + + return val; +} + +static inline uint64_t read64(const volatile void *addr) +{ + uint64_t val; + + /* Set bit to ignore HRMOR */ + addr = (const volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "ldcix %0, 0, %1" : + "=r"(val) : "r"(addr)); + + return val; } static inline void write8(volatile void *addr, uint8_t val) { - *(volatile uint8_t *)addr = val; + /* Set bit to ignore HRMOR */ + addr = (volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "stbcix %0, 0, %1" :: + "r"(val), "r"(addr)); } static inline void write16(volatile void *addr, uint16_t val) { - *(volatile uint16_t *)addr = val; + /* Set bit to ignore HRMOR */ + addr = (volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "sthcix %0, 0, %1" :: + "r"(val), "r"(addr)); } static inline void write32(volatile void *addr, uint32_t val) { - *(volatile uint32_t *)addr = val; + /* Set bit to ignore HRMOR */ + addr = (volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "stwcix %0, 0, %1" :: + "r"(val), "r"(addr)); +} + +static inline void write64(volatile void *addr, uint64_t val) +{ + /* Set bit to ignore HRMOR */ + addr = (volatile void *)((uint64_t)addr | 0x8000000000000000); + asm volatile( + "stdcix %0, 0, %1" :: + "r"(val), "r"(addr)); } #endif /* __ARCH_MMIO_H__ */ |