southbridge/intel/common: Move invalid PIRQ value to 0

This makes structs that contain an `enum pirq` field that is
default-initialized have the value PIRQ_INVALID

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idb4c7d79de13de0e4b187a42e8bdb27e25e61cc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55281
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 30 insertions, 19 deletions

diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 1b6936e508af..0268245f34ba 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -293,14 +293,14 @@ void pch_enable_ioapic(void)
 }
 
 static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = {
-	[PIRQ_A] = PCH_IRQ11,
-	[PIRQ_B] = PCH_IRQ10,
-	[PIRQ_C] = PCH_IRQ11,
-	[PIRQ_D] = PCH_IRQ11,
-	[PIRQ_E] = PCH_IRQ11,
-	[PIRQ_F] = PCH_IRQ11,
-	[PIRQ_G] = PCH_IRQ11,
-	[PIRQ_H] = PCH_IRQ11,
+	[0] = PCH_IRQ11,	/* PIRQ_A */
+	[1] = PCH_IRQ10,	/* PIRQ_B */
+	[2] = PCH_IRQ11,	/* PIRQ_C */
+	[3] = PCH_IRQ11,	/* PIRQ_D */
+	[4] = PCH_IRQ11,	/* PIRQ_E */
+	[5] = PCH_IRQ11,	/* PIRQ_F */
+	[6] = PCH_IRQ11,	/* PIRQ_G */
+	[7] = PCH_IRQ11,	/* PIRQ_H */
 };
 
 const uint8_t *lpc_get_pic_pirq_routing(size_t *num)
diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c
index 852ab85fcb58..102bcb145b28 100644
--- a/src/southbridge/intel/common/acpi_pirq_gen.c
+++ b/src/southbridge/intel/common/acpi_pirq_gen.c
@@ -26,19 +26,20 @@ static void gen_pic_route(const struct slot_pin_irq_map *pin_irq_map,
 			  const struct pic_pirq_map *pirq_map)
 {
 	for (unsigned int i = 0; i < map_count; i++) {
-		enum pirq pirq = pin_irq_map[i].pic_pirq;
-		unsigned int pin = pin_irq_map[i].pin - PCI_INT_A;
+		const enum pirq pirq = pin_irq_map[i].pic_pirq;
+		const unsigned int pin = pin_irq_map[i].pin - PCI_INT_A;
 		if (pirq == PIRQ_INVALID)
 			continue;
 
+		const size_t pirq_index = pirq_idx(pirq);
 		if (pirq_map->type == PIRQ_GSI)
 			acpigen_write_PRT_GSI_entry(pin_irq_map[i].slot,
 						    pin,
-						    pirq_map->gsi[pirq]);
+						    pirq_map->gsi[pirq_index]);
 		else
 			acpigen_write_PRT_source_entry(pin_irq_map[i].slot,
 						       pin,
-						       pirq_map->source_path[pirq],
+						       pirq_map->source_path[pirq_index],
 						       0);
 	}
 }
diff --git a/src/southbridge/intel/common/acpi_pirq_gen.h b/src/southbridge/intel/common/acpi_pirq_gen.h
index 83476d16ca88..4799528fcc3d 100644
--- a/src/southbridge/intel/common/acpi_pirq_gen.h
+++ b/src/southbridge/intel/common/acpi_pirq_gen.h
@@ -3,6 +3,7 @@
 #ifndef INTEL_COMMON_ACPI_PIRQ_GEN_H
 #define INTEL_COMMON_ACPI_PIRQ_GEN_H
 
+#include <assert.h>
 #include <device/device.h>
 
 #define MAX_SLOTS	32
@@ -17,6 +18,7 @@ enum pci_pin {
 };
 
 enum pirq {
+	PIRQ_INVALID,
 	PIRQ_A,
 	PIRQ_B,
 	PIRQ_C,
@@ -25,10 +27,15 @@ enum pirq {
 	PIRQ_F,
 	PIRQ_G,
 	PIRQ_H,
-	PIRQ_COUNT,
-	PIRQ_INVALID = 0xff,
+	PIRQ_COUNT = PIRQ_H,
 };
 
+static inline size_t pirq_idx(enum pirq pirq)
+{
+	assert(pirq > PIRQ_INVALID && pirq <= PIRQ_H);
+	return (size_t)(pirq - PIRQ_A);
+}
+
 /*
  * This struct represents an assignment of slot/pin -> IRQ. Some chipsets may
  * want to provide both PIC-mode and APIC-mode IRQs (e.g. selected using PICM
diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c
index 1037231c34b7..75dad0dc45e4 100644
--- a/src/southbridge/intel/common/rcba_pirq.c
+++ b/src/southbridge/intel/common/rcba_pirq.c
@@ -33,14 +33,14 @@ static enum pirq map_pirq(const struct device *dev, const enum pci_pin pci_pin)
 	/* Slot 24 should not exist and has no D24IR but better be safe here */
 	if (slot < MIN_SLOT || slot > MAX_SLOT || slot == 24) {
 		/* non-PCH devices use 1:1 mapping. */
-		return (enum pirq)(pci_pin - PCI_INT_A);
+		return (enum pirq)pci_pin;
 	}
 
 	reg = pirq_dir_route_reg[slot - MIN_SLOT];
 
 	pirq = (RCBA16(reg) >> shift) & 0x7;
 
-	return (enum pirq)pirq;
+	return (enum pirq)(pirq + PIRQ_A);
 }
 
 void intel_acpi_gen_def_acpi_pirq(const struct device *lpc)
@@ -75,14 +75,17 @@ void intel_acpi_gen_def_acpi_pirq(const struct device *lpc)
 			continue;
 
 		enum pirq pirq = map_pirq(dev, int_pin);
+		if (pirq == PIRQ_INVALID)
+			continue;
+
 		pin_irq_map[map_count].slot = pci_dev;
 		pin_irq_map[map_count].pin = (enum pci_pin)int_pin;
 		pin_irq_map[map_count].pic_pirq = pirq;
 		/* PIRQs are mapped to GSIs starting at 16 */
-		pin_irq_map[map_count].apic_gsi = 16 + (unsigned int)pirq;
-		printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%d\n",
+		pin_irq_map[map_count].apic_gsi = 16 + pirq_idx(pirq);
+		printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%ld\n",
 		       dev_path(dev), int_pin - PCI_INT_A,
-		       pin_irq_map[map_count].pic_pirq);
+		       pirq_idx(pin_irq_map[map_count].pic_pirq));
 		map_count++;
 	}