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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-04 13:50:14 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-08 09:44:56 +0000 |
| commit | ef20ecc92b59b6edc42c06856931a591e71452ac (patch) | |
| tree | 5194abaa9a81bc229010ccaa7c18e22e7494aa95 | |
| parent | 6f027ff28a9b1806343ea253aa04f850fab3e7fb (diff) | |
| download | coreboot-ef20ecc92b59b6edc42c06856931a591e71452ac.tar.gz coreboot-ef20ecc92b59b6edc42c06856931a591e71452ac.tar.bz2 coreboot-ef20ecc92b59b6edc42c06856931a591e71452ac.zip | |
nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address
Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/northbridge/intel/gm45/iommu.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/gma.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 010811666663..f42456413be4 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -46,7 +46,7 @@ void init_iommu() MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */ /* clear GTT */ - u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); + u16 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC); if (gtt & 0x400) { /* VT mode */ pci_devfn_t igd = PCI_DEV(0, 2, 0); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 7de2c73fc98b..a38874a563f9 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -685,7 +685,7 @@ static void i945_setup_pci_express_x16(void) if (reg32 == 0x030000) { printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); reg16 = (1 << 1); - pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16); + pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16); reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN); reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index eb67c659901f..e075ac136c8a 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -98,7 +98,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, gtt_setup(mmio); - pci_write_config16(vga, 0x52, 0x130); + pci_write_config16(vga, GGC, 0x130); /* Disable VGA. */ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); |