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author | Patrick Georgi <patrick@coreboot.org> | 2022-09-08 20:25:46 +0200 |
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committer | Patrick Georgi <patrick@coreboot.org> | 2022-09-17 05:56:34 +0000 |
commit | f0d5f67e46cac62f485805626ca4a7c4dd622a08 (patch) | |
tree | 9f2fefd269f7ef6944335898d1a0116a9ef61133 | |
parent | 2c38933a0e461855c8eab997fc66baffa449f674 (diff) | |
download | coreboot-f0d5f67e46cac62f485805626ca4a7c4dd622a08.tar.gz coreboot-f0d5f67e46cac62f485805626ca4a7c4dd622a08.tar.bz2 coreboot-f0d5f67e46cac62f485805626ca4a7c4dd622a08.zip |
riscv: Enable the newfangled way of selecting instruction sets
gcc12+ will require riscv architecture selection to come not only with
featurei suffixd charactersa, it also comes with feature_ful suffix_ed
words_mith. Much creative, very appreciate.
To accommodate for this madness, enable the already existing (but off by
default) support for that in our gcc11 build, support using by detecting
the compiler's behavior in xcompile and pass that knowledge along to our
build system.
Then cross our fingers and hope for the best!
Change-Id: I5dfeed766626e78d4f8378d9d857b7a4d61510fd
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
-rw-r--r-- | src/arch/riscv/Makefile.inc | 16 | ||||
-rwxr-xr-x | util/crossgcc/buildgcc | 6 | ||||
-rwxr-xr-x | util/xcompile/xcompile | 6 |
3 files changed, 22 insertions, 6 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 272768d02569..bbbdeb07f11f 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -21,19 +21,25 @@ $(error "You need to select ARCH_RISCV_RV64 or ARCH_RISCV_RV32") endif endif +# Needed for -print-libgcc-file-name which gets confused about all those arch +# suffixes in ARCH_SUFFIX_riscv. +simple_riscv_flags = $(riscv_flags) + ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) -riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL) +riscv_flags += -march=$(CONFIG_RISCV_ARCH)$(ARCH_SUFFIX_riscv) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL) +simple_riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL) else riscv_flags += $(_rv_flags) +simple_riscv_flags += $(_rv_flags) endif -riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) +riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH)$(ARCH_SUFFIX_riscv) -mabi=$(CONFIG_RISCV_ABI) -COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(riscv_flags) -print-libgcc-file-name) +COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(simple_riscv_flags) -print-libgcc-file-name) -COMPILER_RT_romstage = $(shell $(GCC_romstage) $(riscv_flags) -print-libgcc-file-name) +COMPILER_RT_romstage = $(shell $(GCC_romstage) $(simple_riscv_flags) -print-libgcc-file-name) -COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(riscv_flags) -print-libgcc-file-name) +COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(simple_riscv_flags) -print-libgcc-file-name) ################################################################################ ## bootblock diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 97d98b197760..a36c25bf1d99 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -681,11 +681,13 @@ build_BINUTILS() { if [ $TARGETARCH = "x86_64-elf" ]; then ADDITIONALTARGET=",i386-elf" fi + # shellcheck disable=SC2086 CC="$(hostcc target)" CXX="$(hostcxx target)" \ ../binutils-${BINUTILS_VERSION}/configure --prefix="$TARGETDIR" \ --target=${TARGETARCH} --enable-targets=${TARGETARCH}${ADDITIONALTARGET} \ --disable-werror --disable-nls --enable-lto \ --enable-gold --enable-multilib \ + ${BINUTILS_OPTIONS} \ CFLAGS="$HOSTCFLAGS" \ CXXFLAGS="$HOSTCFLAGS" \ || touch .failed @@ -932,7 +934,9 @@ case "$TARGETARCH" in x86_64*) TARGETARCH=x86_64-elf;; i386-elf) ;; i386-mingw32) ;; - riscv-elf) TARGETARCH=riscv64-elf;; + riscv-elf) TARGETARCH=riscv64-elf + GCC_OPTIONS="$GCC_OPTIONS --with-isa-spec=20191213" + BINUTILS_OPTIONS="$BINUTILS_OPTIONS --with-isa-spec=20191213";; powerpc64*-linux*) ;; i386*) TARGETARCH=i386-elf;; arm*) TARGETARCH=arm-eabi;; diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index e13996f6b179..e35904fde1dc 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -202,6 +202,10 @@ detect_special_flags() { "$LDFLAGS --fix-cortex-a53-843419" && \ LDFLAGS_ARM64_A53_ERRATUM_843419+=" --fix-cortex-a53-843419" ;; + riscv) + testcc "$GCC" "$FLAGS_GCC -march=rv64iadc_zicsr_zifencei" && + ARCH_SUFFIX="_zicsr_zifencei" + ;; esac } @@ -221,6 +225,7 @@ report_arch_toolchain() { # elf${TWIDTH}-${TBFDARCH} toolchain (${GCC}) ARCH_SUPPORTED+=${TARCH} SUBARCH_SUPPORTED+=${TSUPP-${TARCH}} +ARCH_SUFFIX_${TARCH}:=${ARCH_SUFFIX} # GCC GCC_CC_${TARCH}:=${GCC} @@ -399,6 +404,7 @@ test_architecture() { unset TABI TARCH TBFDARCH TCLIST TENDIAN TSUPP TWIDTH unset CC_RT_EXTRA_GCC CC_RT_EXTRA_CLANG unset GCC CLANG + unset ARCH_SUFFIX if type "arch_config_$architecture" > /dev/null; then "arch_config_$architecture" else |