soc/intel/skylake: switch to common ACPI code

Use the common ACPI code to reduce code duplication.

After this change, `PSS_MAX_ENTRIES` is honored correctly in P-state
table generation (as of commit c2540a9) and the number reduces from 10
to 7 entries.

Also, remnants of P_BLK support missed in CB:58096 will vanish.

Tested on google/fizz: no errors in dmesg, ACPI tables remain the same
(except PSS, as mentioned above).

Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

9 files changed, 64 insertions, 426 deletions

diff --git a/src/mainboard/supermicro/x11-lga1151-series/fadt.c b/src/mainboard/supermicro/x11-lga1151-series/fadt.c
index 6306e03e307c..0686f7ad20a5 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/fadt.c
+++ b/src/mainboard/supermicro/x11-lga1151-series/fadt.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
-#include <soc/acpi.h>
+#include <intelblocks/acpi.h>
 
 void mainboard_fill_fadt(acpi_fadt_t *fadt)
 {
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index d66c331064dd..bd3353d50e96 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -51,6 +51,8 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK
+	select SOC_INTEL_COMMON_BLOCK_ACPI
+	select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
 	select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
 	select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
 	select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 72c5e472de0a..cac72532ea9a 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -8,33 +8,22 @@
 #include <arch/ioapic.h>
 #include <arch/smp/mpspec.h>
 #include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <cpu/x86/msr.h>
 #include <cpu/intel/common/common.h>
-#include <cpu/intel/turbo.h>
+#include <intelblocks/acpi.h>
 #include <intelblocks/acpi_wake_source.h>
 #include <intelblocks/cpulib.h>
-#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pmclib.h>
 #include <intelblocks/sgx.h>
-#include <intelblocks/uart.h>
-#include <intelblocks/systemagent.h>
-#include <soc/acpi.h>
 #include <soc/cpu.h>
-#include <soc/iomap.h>
 #include <soc/msr.h>
-#include <soc/nvs.h>
-#include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/systemagent.h>
 #include <string.h>
 #include <types.h>
-#include <device/pci_ops.h>
 
 #include "chip.h"
 
-#define  CPUID_6_EAX_ISST	(1 << 7)
-
 /*
  * List of supported C-states in this processor.
  */
@@ -139,271 +128,65 @@ static int cstate_set_non_s0ix[] = {
 	C_STATE_C7S_LONG_LAT,
 };
 
-static int get_cores_per_package(void)
-{
-	struct cpuinfo_x86 c;
-	struct cpuid_result result;
-	int cores = 1;
-
-	get_fms(&c, cpuid_eax(1));
-	if (c.x86 != 6)
-		return 1;
-
-	result = cpuid_ext(0xb, 1);
-	cores = result.ebx & 0xff;
-
-	return cores;
-}
-
-void soc_fill_gnvs(struct global_nvs *gnvs)
-{
-	const struct soc_intel_skylake_config *config = config_of_soc();
-
-	/* Enable DPTF based on mainboard configuration */
-	gnvs->dpte = config->dptf_enable;
-
-	/* Set USB2/USB3 wake enable bitmaps. */
-	gnvs->u2we = config->usb2_wake_enable_bitmap;
-	gnvs->u3we = config->usb3_wake_enable_bitmap;
-
-	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
-		sgx_fill_gnvs(gnvs);
-
-	/* Fill in Above 4GB MMIO resource */
-	sa_fill_gnvs(gnvs);
-}
-
-unsigned long acpi_fill_mcfg(unsigned long current)
+acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 {
-	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
-					     CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
-					     CONFIG_MMCONF_BUS_NUMBER - 1);
-	return current;
-}
+	static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
+				ARRAY_SIZE(cstate_set_non_s0ix))];
+	int *set;
+	int i;
 
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
+	config_t *config = config_of_soc();
 
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
+	int is_s0ix_enable = config->s0ix_enable;
 
-	return acpi_madt_irq_overrides(current);
-}
+	if (is_s0ix_enable) {
+		*entries = ARRAY_SIZE(cstate_set_s0ix);
+		set = cstate_set_s0ix;
+	} else {
+		*entries = ARRAY_SIZE(cstate_set_non_s0ix);
+		set = cstate_set_non_s0ix;
+	}
 
-static void write_c_state_entries(acpi_cstate_t *map, const int *set, size_t max_c_state)
-{
-	for (size_t i = 0; i < max_c_state; i++) {
+	for (i = 0; i < *entries; i++) {
 		memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));
 		map[i].ctype = i + 1;
 	}
-
-	/* Generate C-state tables */
-	acpigen_write_CST_package(map, max_c_state);
+	return map;
 }
 
-static void generate_c_state_entries(int s0ix_enable)
+void soc_power_states_generation(int core_id, int cores_per_package)
 {
-	if (s0ix_enable) {
-		acpi_cstate_t map[ARRAY_SIZE(cstate_set_s0ix)];
-		write_c_state_entries(map, cstate_set_s0ix, ARRAY_SIZE(map));
-	} else {
-		acpi_cstate_t map[ARRAY_SIZE(cstate_set_non_s0ix)];
-		write_c_state_entries(map, cstate_set_non_s0ix, ARRAY_SIZE(map));
-	}
-}
-
-static int calculate_power(int tdp, int p1_ratio, int ratio)
-{
-	u32 m;
-	u32 power;
-
-	/*
-	 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
-	 *
-	 * Power = (ratio / p1_ratio) * m * tdp
-	 */
-
-	m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
-	m = (m * m) / 1000;
-
-	power = ((ratio * 100000 / p1_ratio) / 100);
-	power *= (m / 100) * (tdp / 1000);
-	power /= 1000;
+	config_t *config = config_of_soc();
 
-	return (int)power;
+	/* Generate P-state tables */
+	if (config->eist_enable)
+		generate_p_state_entries(core_id, cores_per_package);
 }
 
-static void generate_p_state_entries(int core, int cores_per_package)
+uint32_t soc_read_sci_irq_select(void)
 {
-	int ratio_min, ratio_max, ratio_turbo, ratio_step;
-	int coord_type, power_max, power_unit, num_entries;
-	int ratio, power, clock, clock_max;
-	msr_t msr;
-
-	/* Determine P-state coordination type from MISC_PWR_MGMT[0] */
-	msr = rdmsr(MSR_MISC_PWR_MGMT);
-	if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
-		coord_type = SW_ANY;
-	else
-		coord_type = HW_ALL;
-
-	/* Get bus ratio limits and calculate clock speeds */
-	msr = rdmsr(MSR_PLATFORM_INFO);
-	ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
-
-	/* Determine if this CPU has configurable TDP */
-	if (cpu_config_tdp_levels()) {
-		/* Set max ratio to nominal TDP ratio */
-		msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
-		ratio_max = msr.lo & 0xff;
-	} else {
-		/* Max Non-Turbo Ratio */
-		ratio_max = (msr.lo >> 8) & 0xff;
-	}
-	clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ;
-
-	/* Calculate CPU TDP in mW */
-	msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
-	power_unit = 2 << ((msr.lo & 0xf) - 1);
-	msr = rdmsr(MSR_PKG_POWER_SKU);
-	power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
-
-	/* Write _PCT indicating use of FFixedHW */
-	acpigen_write_empty_PCT();
-
-	/* Write _PPC with no limit on supported P-state */
-	acpigen_write_PPC_NVS();
-
-	/* Write PSD indicating configured coordination type */
-	acpigen_write_PSD_package(core, 1, coord_type);
-
-	/* Add P-state entries in _PSS table */
-	acpigen_write_name("_PSS");
-
-	/* Determine ratio points */
-	ratio_step = PSS_RATIO_STEP;
-	num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
-	if (num_entries > PSS_MAX_ENTRIES) {
-		ratio_step += 1;
-		num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
-	}
-
-	/* P[T] is Turbo state if enabled */
-	if (get_turbo_state() == TURBO_ENABLED) {
-		/* _PSS package count including Turbo */
-		acpigen_write_package(num_entries + 2);
-
-		msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
-		ratio_turbo = msr.lo & 0xff;
-
-		/* Add entry for Turbo ratio */
-		acpigen_write_PSS_package(
-			clock_max + 1,		/* MHz */
-			power_max,		/* mW */
-			PSS_LATENCY_TRANSITION,	/* lat1 */
-			PSS_LATENCY_BUSMASTER,	/* lat2 */
-			ratio_turbo << 8,	/* control */
-			ratio_turbo << 8);	/* status */
-	} else {
-		/* _PSS package count without Turbo */
-		acpigen_write_package(num_entries + 1);
-	}
-
-	/* First regular entry is max non-turbo ratio */
-	acpigen_write_PSS_package(
-		clock_max,		/* MHz */
-		power_max,		/* mW */
-		PSS_LATENCY_TRANSITION,	/* lat1 */
-		PSS_LATENCY_BUSMASTER,	/* lat2 */
-		ratio_max << 8,		/* control */
-		ratio_max << 8);	/* status */
-
-	/* Generate the remaining entries */
-	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
-	     ratio >= ratio_min; ratio -= ratio_step) {
-
-		/* Calculate power at this ratio */
-		power = calculate_power(power_max, ratio_max, ratio);
-		clock = ratio * CONFIG_CPU_BCLK_MHZ;
-
-		acpigen_write_PSS_package(
-			clock,			/* MHz */
-			power,			/* mW */
-			PSS_LATENCY_TRANSITION,	/* lat1 */
-			PSS_LATENCY_BUSMASTER,	/* lat2 */
-			ratio << 8,		/* control */
-			ratio << 8);		/* status */
-	}
-
-	/* Fix package length */
-	acpigen_pop_len();
+	return read32p(soc_read_pmc_base() + IRQ_REG);
 }
 
-static void generate_cppc_entries(int core_id)
+void soc_fill_gnvs(struct global_nvs *gnvs)
 {
-	/* Generate GCPC table in first logical core */
-	if (core_id == 0) {
-		struct cppc_config cppc_config;
-		cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2);
-		acpigen_write_CPPC_package(&cppc_config);
-	}
+	const struct soc_intel_skylake_config *config = config_of_soc();
 
-	/* Write _CST entry for each logical core */
-	acpigen_write_CPPC_method();
-}
+	/* Enable DPTF based on mainboard configuration */
+	gnvs->dpte = config->dptf_enable;
 
-void generate_cpu_entries(const struct device *device)
-{
-	int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6;
-	int totalcores = dev_count_cpu();
-	int cores_per_package = get_cores_per_package();
-	int numcpus = totalcores/cores_per_package;
-	config_t *config = config_of_soc();
-	int is_s0ix_enable = config->s0ix_enable;
-	const bool isst_supported = cpuid_eax(6) & CPUID_6_EAX_ISST;
-
-	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
-	       numcpus, cores_per_package);
-
-	for (cpu_id = 0; cpu_id < numcpus; cpu_id++) {
-		for (core_id = 0; core_id < cores_per_package; core_id++) {
-			if (core_id > 0) {
-				pcontrol_blk = 0;
-				plen = 0;
-			}
-
-			/* Generate processor \_SB.CPUx */
-			acpigen_write_processor(
-				cpu_id*cores_per_package+core_id,
-				pcontrol_blk, plen);
-			/* Generate C-state tables */
-			generate_c_state_entries(is_s0ix_enable);
-
-			if (config->eist_enable) {
-				/* Generate P-state tables */
-				generate_p_state_entries(core_id,
-						cores_per_package);
-			}
-
-			if (isst_supported)
-				generate_cppc_entries(core_id);
-
-			acpigen_pop_len();
-		}
-	}
+	/* Set USB2/USB3 wake enable bitmaps. */
+	gnvs->u2we = config->usb2_wake_enable_bitmap;
+	gnvs->u3we = config->usb3_wake_enable_bitmap;
 
-	/* PPKG is usually used for thermal management
-	   of the first and only package. */
-	acpigen_write_processor_package("PPKG", 0, cores_per_package);
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
+		sgx_fill_gnvs(gnvs);
 
-	/* Add a method to notify processor nodes */
-	acpigen_write_processor_cnot(cores_per_package);
+	/* Fill in Above 4GB MMIO resource */
+	sa_fill_gnvs(gnvs);
 }
 
-static unsigned long acpi_fill_dmar(unsigned long current)
+static unsigned long soc_fill_dmar(unsigned long current)
 {
 	const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
 	const bool gfxvten = MCHBAR32(GFXVTBAR) & 1;
@@ -455,9 +238,9 @@ static unsigned long acpi_fill_dmar(unsigned long current)
 	return current;
 }
 
-unsigned long northbridge_write_acpi_tables(const struct device *const dev,
-					    unsigned long current,
-					    struct acpi_rsdp *const rsdp)
+unsigned long sa_write_acpi_tables(const struct device *const dev,
+				   unsigned long current,
+				   struct acpi_rsdp *const rsdp)
 {
 	acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
 
@@ -466,7 +249,7 @@ unsigned long northbridge_write_acpi_tables(const struct device *const dev,
 		return current;
 
 	printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
-	acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
+	acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar);
 	current += dmar->header.length;
 	current = acpi_align_current(current);
 	acpi_add_table(rsdp, dmar);
@@ -474,103 +257,23 @@ unsigned long northbridge_write_acpi_tables(const struct device *const dev,
 	return current;
 }
 
-int acpi_sci_irq(void)
-{
-	int scis = pci_read_config32(PCH_DEV_PMC, ACTL) & SCI_IRQ_SEL;
-	int sci_irq = 9;
-
-	/* Determine how SCI is routed. */
-	switch (scis) {
-	case SCIS_IRQ9:
-	case SCIS_IRQ10:
-	case SCIS_IRQ11:
-		sci_irq = scis - SCIS_IRQ9 + 9;
-		break;
-	case SCIS_IRQ20:
-	case SCIS_IRQ21:
-	case SCIS_IRQ22:
-	case SCIS_IRQ23:
-		sci_irq = scis - SCIS_IRQ20 + 20;
-		break;
-	default:
-		printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
-		sci_irq = 9;
-		break;
-	}
-
-	printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
-	return sci_irq;
-}
-
-unsigned long acpi_madt_irq_overrides(unsigned long current)
+int soc_madt_sci_irq_polarity(int sci)
 {
-	int sci = acpi_sci_irq();
-	acpi_madt_irqoverride_t *irqovr;
-	uint16_t flags = MP_IRQ_TRIGGER_LEVEL;
-
-	/* INT_SRC_OVR */
-	irqovr = (void *)current;
-	current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
-
 	if (sci >= 20)
-		flags |= MP_IRQ_POLARITY_LOW;
+		return MP_IRQ_POLARITY_LOW;
 	else
-		flags |= MP_IRQ_POLARITY_HIGH;
-
-	/* SCI */
-	irqovr = (void *)current;
-	current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags);
-
-	/* NMI */
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
-
-	return current;
-}
-
-unsigned long southbridge_write_acpi_tables(const struct device *device,
-					     unsigned long current,
-					     struct acpi_rsdp *rsdp)
-{
-	current = acpi_write_dbg2_pci_uart(rsdp, current,
-					   uart_get_device(),
-					   ACPI_ACCESS_SIZE_DWORD_ACCESS);
-	current = acpi_write_hpet(device, current, rsdp);
-	return acpi_align_current(current);
+		return MP_IRQ_POLARITY_HIGH;
 }
 
-/* Save wake source information for calculating ACPI _SWS values */
-int soc_fill_acpi_wake(const struct chipset_power_state *ps, uint32_t *pm1, uint32_t **gpe0)
+void acpi_fill_soc_wake(uint32_t *pm1_en, uint32_t *gpe0_en,
+			const struct chipset_power_state *ps)
 {
 	const struct soc_intel_skylake_config *config = config_of_soc();
-	static uint32_t gpe0_sts[GPE0_REG_MAX];
-	uint32_t pm1_en;
-	uint32_t gpe0_std;
-	int i;
-	const int last_index = GPE0_REG_MAX - 1;
-
-	pm1_en = ps->pm1_en;
-	gpe0_std = ps->gpe0_en[3];
-
-	/*
-	 * Chipset state in the suspend well (but not RTC) is lost in Deep S3
-	 * so enable Deep S3 wake events that are configured by the mainboard
-	 */
-	if (ps->prev_sleep_state == ACPI_S3 &&
-	    (config->deep_s3_enable_ac || config->deep_s3_enable_dc)) {
-		pm1_en |= PWRBTN_STS; /* Always enabled as wake source */
+
+	if (ps->prev_sleep_state == ACPI_S3 && deep_s3_enabled()) {
 		if (config->deep_sx_config & DSX_EN_LAN_WAKE_PIN)
-			gpe0_std |= LAN_WAK_EN;
+			gpe0_en[GPE_STD] |= LAN_WAK_EN;
 		if (config->deep_sx_config & DSX_EN_WAKE_PIN)
-			pm1_en |= PCIEXPWAK_STS;
+			*pm1_en |= PCIEXPWAK_STS;
 	}
-
-	*pm1 = ps->pm1_sts & pm1_en;
-
-	/* Mask off GPE0 status bits that are not enabled */
-	*gpe0 = &gpe0_sts[0];
-	for (i = 0; i < last_index; i++)
-		gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
-	gpe0_sts[last_index] = ps->gpe0_sts[last_index] & gpe0_std;
-
-	return GPE0_REG_MAX;
 }
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index d706e1298d1b..dd42f31961de 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -10,6 +10,7 @@
 #include <fsp/util.h>
 #include <gpio.h>
 #include <option.h>
+#include <intelblocks/acpi.h>
 #include <intelblocks/cfg.h>
 #include <intelblocks/itss.h>
 #include <intelblocks/lpc_lib.h>
@@ -18,7 +19,6 @@
 #include <intelblocks/xdci.h>
 #include <intelblocks/p2sb.h>
 #include <intelpch/lockdown.h>
-#include <soc/acpi.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/interrupt.h>
 #include <soc/iomap.h>
@@ -191,7 +191,6 @@ static struct device_operations pci_domain_ops = {
 	.set_resources    = &pci_domain_set_resources,
 	.scan_bus         = &pci_domain_scan_bus,
 #if CONFIG(HAVE_ACPI_TABLES)
-	.write_acpi_tables	= &northbridge_write_acpi_tables,
 	.acpi_name		= &soc_acpi_name,
 #endif
 };
diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c
index 61e9417abd11..774dd5e1f57d 100644
--- a/src/soc/intel/skylake/fadt.c
+++ b/src/soc/intel/skylake/fadt.c
@@ -2,68 +2,28 @@
 
 #include <acpi/acpi.h>
 #include <cpu/x86/smm.h>
-#include <soc/acpi.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
 #include "chip.h"
 
-void acpi_fill_fadt(acpi_fadt_t *fadt)
+void soc_fill_fadt(acpi_fadt_t *fadt)
 {
 	const uint16_t pmbase = ACPI_BASE_ADDRESS;
 	config_t *config = config_of_soc();
 
-	fadt->header.revision = get_acpi_table_revision(FADT);
-
-	fadt->sci_int = acpi_sci_irq();
-
-	if (permanent_smi_handler()) {
-		fadt->smi_cmd = APM_CNT;
-		fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
-		fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
-	}
-
-	fadt->pm1a_evt_blk = pmbase + PM1_STS;
-	fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
 	fadt->pm2_cnt_blk = pmbase + PM2_CNT;
 	fadt->pm_tmr_blk = pmbase + PM1_TMR;
-	fadt->gpe0_blk = pmbase + GPE0_STS(0);
 
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
 	fadt->pm2_cnt_len = 1;
 	fadt->pm_tmr_len = 4;
-	/* There are 4 GPE0 STS/EN pairs each 32 bits wide. */
-	fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
-	fadt->day_alrm = 0xd;
-	fadt->mon_alrm = 0x00;
+
 	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE;
 	if (!CONFIG(NO_FADT_8042))
 		fadt->iapc_boot_arch |= ACPI_FADT_8042;
 
-	fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
-			ACPI_FADT_SLEEP_BUTTON |
-			ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE;
-
-	if (CONFIG(USE_PM_ACPI_TIMER))
-		fadt->flags |= ACPI_FADT_PLATFORM_CLOCK;
-
 	if (config->s0ix_enable)
 		fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 
-	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
-	fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
-	fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
 	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
 	fadt->x_pm2_cnt_blk.bit_offset = 0;
@@ -77,17 +37,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 	fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
 	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-	/*
-	 * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5.
-	 * The bit_width field intentionally overflows here.
-	 * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which
-	 * seems to work fine on Linux 5.0 and Windows 10.
-	 */
-	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
-	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
-	fadt->x_gpe0_blk.addrh = 0;
 }
diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h
deleted file mode 100644
index 683a50490ae8..000000000000
--- a/src/soc/intel/skylake/include/soc/acpi.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SOC_ACPI_H_
-#define _SOC_ACPI_H_
-
-#include <acpi/acpi.h>
-
-/* P-state configuration */
-#define PSS_MAX_ENTRIES			8
-#define PSS_RATIO_STEP			2
-#define PSS_LATENCY_TRANSITION		10
-#define PSS_LATENCY_BUSMASTER		10
-
-/* Return the selected ACPI SCI IRQ */
-int acpi_sci_irq(void);
-unsigned long acpi_madt_irq_overrides(unsigned long current);
-unsigned long northbridge_write_acpi_tables(const struct device *,
-	unsigned long current, struct acpi_rsdp *);
-
-#endif /* _SOC_ACPI_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index a57772446eab..f0ce14656230 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -141,6 +141,12 @@
 
 #define PRSTS		0x10
 
+/* P-state configuration */
+#define PSS_MAX_ENTRIES		8
+#define PSS_RATIO_STEP		2
+#define PSS_LATENCY_TRANSITION	10
+#define PSS_LATENCY_BUSMASTER	10
+
 struct chipset_power_state {
 	uint16_t pm1_sts;
 	uint16_t pm1_en;
diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h
index 8fe3f83cadf1..165d57170ee7 100644
--- a/src/soc/intel/skylake/include/soc/pmc.h
+++ b/src/soc/intel/skylake/include/soc/pmc.h
@@ -59,6 +59,8 @@
 #define ETR3			0xac
 #define  ETR3_CF9LOCK		(1 << 31)
 #define  ETR3_CF9GR		(1 << 20)
+#define SCI_IRQ_ADJUST		0
+#define IRQ_REG			ACTL
 
 /* Memory mapped IO registers in PMC */
 #define S3_PWRGATE_POL		0x28
diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h
index 02d53a1e17db..a5e6930bec9f 100644
--- a/src/soc/intel/skylake/include/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/soc/ramstage.h
@@ -15,6 +15,5 @@
 void mainboard_silicon_init_params(FSP_S_CONFIG *params);
 void soc_init_pre_device(void *chip_info);
 void soc_irq_settings(FSP_SIL_UPD *params);
-const char *soc_acpi_name(const struct device *dev);
 
 #endif