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| author | Chris.Wang <chris.wang@amd.corp-partner.google.com> | 2023-03-16 15:11:36 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-29 13:20:25 +0000 |
| commit | f83b282856ebf83194fd7e2bd7adb5e65a2bd384 (patch) | |
| tree | b0b92b8d371ff3df1a2f562a4558cb5a6e8585a2 | |
| parent | 8f2953b279d6cb1b73c791412818e144e253175b (diff) | |
| download | coreboot-f83b282856ebf83194fd7e2bd7adb5e65a2bd384.tar.gz coreboot-f83b282856ebf83194fd7e2bd7adb5e65a2bd384.tar.bz2 coreboot-f83b282856ebf83194fd7e2bd7adb5e65a2bd384.zip | |
soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment
Add UPD parameter for eDP power sequence adjust.
The pwr_on_vary_bl_to_blon is set one unit per 4ms.
BUG=b:271704149
TEST=Build; Verify the UPD was pass to system integrated table;
measure the power on sequence on whiterun
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I25c9f962e70f599c780259f0943a03f8aa7cbfd1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
| -rw-r--r-- | src/soc/amd/mendocino/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/fsp_m_params.c | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index f16f5fd4bebc..774ce5ea5908 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -177,6 +177,10 @@ struct soc_amd_mendocino_config { /* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */ union usb3_force_gen1 usb3_port_force_gen1; + /* Set for eDP power sequence adjustment timing from varybl to blon. The unit is set to + one per 4ms*/ + uint8_t pwr_on_vary_bl_to_blon; + }; #endif /* MENDOCINO_CHIP_H */ diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c index 37d4048a8027..453ce69788c0 100644 --- a/src/soc/amd/mendocino/fsp_m_params.c +++ b/src/soc/amd/mendocino/fsp_m_params.c @@ -170,6 +170,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) } mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable; + mcfg->pwr_on_vary_bl_to_blon = config->pwr_on_vary_bl_to_blon; fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); |