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authorRex-BC Chen <rex-bc.chen@mediatek.com>2022-07-28 16:38:53 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-08-03 16:40:20 +0000
commitf9009dde545bc96840f381afc3170818a0d91e29 (patch)
treed5b0a1c96931c716da27ba3e062f73490e9b897b
parentd9e568a0464796b0d5e6209f4c5e3d7ed42e59b2 (diff)
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mb/google/geralt: Configure GPIOs
Configure ChromeOS specific GPIOs: - Open-drain pins to high-z mode: GPIO_EC_AP_INT_ODL, GPIO_GSC_AP_INT_ODL and GPIO_WP_ODL. - GPO mode: GPIO_AP_EC_WARM_RST_REQ, GPIO_EN_SPKR and GPIO_XHCI_INIT_DONE. This patch is based on MT8188G_GPIO_Formal_Application_Spec_V0.3. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I84d3f62ec8a3966fe1982d5d4cf6ff270450d4bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/66274 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/geralt/bootblock.c1
-rw-r--r--src/mainboard/google/geralt/chromeos.c20
-rw-r--r--src/mainboard/google/geralt/gpio.h5
3 files changed, 25 insertions, 1 deletions
diff --git a/src/mainboard/google/geralt/bootblock.c b/src/mainboard/google/geralt/bootblock.c
index 9a76b368ca0..4476aab2b88 100644
--- a/src/mainboard/google/geralt/bootblock.c
+++ b/src/mainboard/google/geralt/bootblock.c
@@ -13,5 +13,6 @@ void bootblock_mainboard_init(void)
mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST);
mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
mtk_snfc_init();
+ setup_chromeos_gpios();
gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING);
}
diff --git a/src/mainboard/google/geralt/chromeos.c b/src/mainboard/google/geralt/chromeos.c
index eb93be20c4d..1723e6bfa87 100644
--- a/src/mainboard/google/geralt/chromeos.c
+++ b/src/mainboard/google/geralt/chromeos.c
@@ -7,9 +7,27 @@
#include "gpio.h"
+void setup_chromeos_gpios(void)
+{
+ /* Set up open-drain pins */
+ gpio_input(GPIO_EC_AP_INT_ODL);
+ gpio_input(GPIO_GSC_AP_INT_ODL);
+ gpio_input(GPIO_AP_WP_ODL);
+
+ /* Set up GPOs */
+ gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0);
+ gpio_output(GPIO_EN_SPKR, 0);
+ gpio_output(GPIO_XHCI_INIT_DONE, 0);
+}
+
void fill_lb_gpios(struct lb_gpios *gpios)
{
- /* TODO: add Chrome specific gpios */
+ struct lb_gpio chromeos_gpios[] = {
+ {GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt"},
+ {GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt"},
+ {GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
int tis_plat_irq_status(void)
diff --git a/src/mainboard/google/geralt/gpio.h b/src/mainboard/google/geralt/gpio.h
index ff6de175630..5be09ce4792 100644
--- a/src/mainboard/google/geralt/gpio.h
+++ b/src/mainboard/google/geralt/gpio.h
@@ -6,7 +6,12 @@
#include <soc/gpio.h>
#define GPIO_AP_EC_WARM_RST_REQ GPIO(DPI_HSYNC)
+#define GPIO_AP_WP_ODL GPIO(GPIO15)
+#define GPIO_BEEP_ON_OD GPIO(I2SIN_WS)
+#define GPIO_EC_AP_INT_ODL GPIO(DPI_DE)
+#define GPIO_EN_SPKR GPIO(I2SIN_D2)
#define GPIO_GSC_AP_INT_ODL GPIO(GPIO00)
+#define GPIO_XHCI_INIT_DONE GPIO(DPI_CK)
void setup_chromeos_gpios(void);