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| author | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2022-09-22 14:41:22 -0500 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-10-30 17:00:45 +0000 |
| commit | f90ff456fc5ede4cefaca5915602217ebff9e9a2 (patch) | |
| tree | 723a848708fdd2b3c368ca011d5d55912571d465 | |
| parent | aa8796d3fd10ab52f2f6d3c7aa1684c72c08fc8c (diff) | |
| download | coreboot-f90ff456fc5ede4cefaca5915602217ebff9e9a2.tar.gz coreboot-f90ff456fc5ede4cefaca5915602217ebff9e9a2.tar.bz2 coreboot-f90ff456fc5ede4cefaca5915602217ebff9e9a2.zip | |
mb/google/skyrim: Implement touchscreen power sequencing
Assuming variants have a touchscreen by default, set the enable GPIO
high and hold in reset during romstage, then release reset in ramstage.
This will allow the touchscreen to make use of the runtime I2C detect
feature (enabled in a subsequent commit) so that an ACPI device entry
is created only for the touchscreen actually present.
Variants/SKUs which do not have a touchscreen (if any) can use the
romstage/ramstage GPIO override tables to set the associated enable/
reset GPIOs to NC.
BUG=b:121309055
TEST=build/boot skyrim with rest of patch series
Change-Id: Ic4d7ac8f951bb94da2216a24dc85a96275c9d449
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/mainboard/google/skyrim/variants/baseboard/gpio.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index 6062d935c230..2e265d18ebc5 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -113,10 +113,11 @@ static const struct soc_amd_gpio base_gpio_table[] = { PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), /* SOC_FPMCU_BOOT0 */ PAD_GPO(GPIO_130, LOW), + /* Enable touchscreen, release from reset */ /* EN_PP3300_TCHSCR */ - PAD_GPO(GPIO_131, LOW), + PAD_GPO(GPIO_131, HIGH), /* TCHSCR_RESET_L */ - PAD_GPO(GPIO_136, LOW), + PAD_GPO(GPIO_136, HIGH), /* SOC_BIOS_WP_L */ PAD_GPI(GPIO_138, PULL_NONE), /* EN_SPKR */ @@ -200,6 +201,11 @@ static const struct soc_amd_gpio romstage_gpio_table[] = { PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), /* SSD_AUX_RESET_L */ PAD_GPO(GPIO_6, HIGH), + /* Enable touchscreen, hold in reset */ + /* EN_PP3300_TCHSCR */ + PAD_GPO(GPIO_131, HIGH), + /* TCHSCR_RESET_L */ + PAD_GPO(GPIO_136, LOW), }; void baseboard_romstage_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) |