diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-12-16 15:07:15 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-07 19:59:29 +0000 |
| commit | f94405219c93613471a33db9a76bb6106469eb1b (patch) | |
| tree | 7ded07db717e532a726f3d4499c68a759f6ed403 | |
| parent | ef5f7ee696097174f9d1f01e9b04ea8f1354cfe0 (diff) | |
| download | coreboot-f94405219c93613471a33db9a76bb6106469eb1b.tar.gz coreboot-f94405219c93613471a33db9a76bb6106469eb1b.tar.bz2 coreboot-f94405219c93613471a33db9a76bb6106469eb1b.zip | |
soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs
The Alder Lake chip.h file has pcie_rp_config entries for the CPU PCIe
ports, but the UPDs are not set. This patch hooks up those config
structs to the appropriate FSP-S UPDs.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibb2375e66d53b4b7567dbe88b941cd720fdad927
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 251b25262a31..2ab896500d05 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -615,6 +615,27 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, } } +static void fill_fsps_cpu_pcie_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_alderlake_config *config) +{ + if (!CONFIG_MAX_CPU_ROOT_PORTS) + return; + + const uint32_t enable_mask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); + for (int i = 0; i < CONFIG_MAX_CPU_ROOT_PORTS; i++) { + if (!(enable_mask & BIT(i))) + continue; + + const struct pcie_rp_config *rp_cfg = &config->cpu_pcie_rp[i]; + s_cfg->CpuPcieRpL1Substates[i] = + get_l1_substate_control(rp_cfg->PcieRpL1Substates); + s_cfg->CpuPcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); + s_cfg->CpuPcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); + s_cfg->CpuPcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); + s_cfg->PtmEnabled[i] = 0; + } +} + static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { @@ -783,6 +804,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, fill_fsps_pm_timer_params, fill_fsps_storage_params, fill_fsps_pcie_params, + fill_fsps_cpu_pcie_params, fill_fsps_misc_power_params, fill_fsps_irq_params, fill_fsps_fivr_params, |