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| author | Sean Rhodes <sean@starlabs.systems> | 2023-08-30 13:14:21 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-22 13:39:06 +0000 |
| commit | fb401e74da0cd03ef2ee9dc8b2dc8863a5c25a84 (patch) | |
| tree | b518b592077d0b6af94133280b535033629c5541 | |
| parent | b8f49c6d380c6a07e8addd3910b4730c9e14840b (diff) | |
| download | coreboot-fb401e74da0cd03ef2ee9dc8b2dc8863a5c25a84.tar.gz coreboot-fb401e74da0cd03ef2ee9dc8b2dc8863a5c25a84.tar.bz2 coreboot-fb401e74da0cd03ef2ee9dc8b2dc8863a5c25a84.zip | |
soc/intel/alderlake: Sync UPD Usb4CmMode with Kconfig
The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set
the UPD to match this to avoid the connection type being mismatched.
If it's mismatched, the TBT port will time out.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8a99db165301ce08caf55aac0e33ca1994559d62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80486
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index cb5459868a3a..d9c0f8e4d64a 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -679,6 +679,10 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, if (is_dev_enabled(tcss_port_arr[i])) s_cfg->UsbTcPortEn |= BIT(i); } + +#if !CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) + s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER); +#endif } static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, |