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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-03-31 15:01:16 +1100 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-04-02 01:07:27 +0200 |
| commit | fbdc3ef7d9df3b68efafffa1c2d50352d25dfb60 (patch) | |
| tree | 9c02ade6ca17f64f7e3fbd35b6d70f11ceb0707a | |
| parent | 905bfb05dc3f6063c396d4665cc95dcde91a8ced (diff) | |
| download | coreboot-fbdc3ef7d9df3b68efafffa1c2d50352d25dfb60.tar.gz coreboot-fbdc3ef7d9df3b68efafffa1c2d50352d25dfb60.tar.bz2 coreboot-fbdc3ef7d9df3b68efafffa1c2d50352d25dfb60.zip | |
superio/fintek/f71805f: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.
Change-Id: Ibf743f7a5dd4a424a4513014fc9a896b87ecf3b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5434
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
| -rw-r--r-- | src/mainboard/jetway/j7f2/romstage.c | 2 | ||||
| -rw-r--r-- | src/superio/fintek/f71805f/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/superio/fintek/f71805f/early_serial.c | 3 | ||||
| -rw-r--r-- | src/superio/fintek/f71805f/f71805f.h | 4 |
4 files changed, 7 insertions, 4 deletions
diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index 928fcef992d4..37c3ab4186c7 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -31,7 +31,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" -#include "superio/fintek/f71805f/early_serial.c" +#include <superio/fintek/f71805f/f71805f.h> #include <lib.h> #include <spd.h> diff --git a/src/superio/fintek/f71805f/Makefile.inc b/src/superio/fintek/f71805f/Makefile.inc index 9ed5e6f9f814..22c01e059ce9 100644 --- a/src/superio/fintek/f71805f/Makefile.inc +++ b/src/superio/fintek/f71805f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += superio.c - diff --git a/src/superio/fintek/f71805f/early_serial.c b/src/superio/fintek/f71805f/early_serial.c index 827f870a3727..b823a430e52c 100644 --- a/src/superio/fintek/f71805f/early_serial.c +++ b/src/superio/fintek/f71805f/early_serial.c @@ -21,6 +21,7 @@ /* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */ #include <arch/io.h> +#include <device/pnp.h> #include "f71805f.h" static void pnp_enter_conf_state(device_t dev) @@ -36,7 +37,7 @@ static void pnp_exit_conf_state(device_t dev) outb(0xaa, port); } -static void f71805f_enable_serial(device_t dev, u16 iobase) +void f71805f_enable_serial(device_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/fintek/f71805f/f71805f.h b/src/superio/fintek/f71805f/f71805f.h index 0670128da102..6aae58f299f6 100644 --- a/src/superio/fintek/f71805f/f71805f.h +++ b/src/superio/fintek/f71805f/f71805f.h @@ -38,4 +38,6 @@ #define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ #define F71805F_PME 0x0a /* Power Management Events (PME) */ -#endif +void f71805f_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_FINTEK_F71805F_F71805F_H */ |